Hierarchical power routing

Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements

Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. 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Propulsion, energy collection, communication or habitation in space requires ever larger space structures for the exploration of our solar system and beyond. Due to the payload size restrictions of the current launch vehicles, deployable structures are the way to go to launch very large structures into orbit. This paper therefore presents the design and simulation of a tensegrity based structure with inflatable rigidizable tubes as compression struts. The literature review showed that inflatable structures are most promising for the development of deployable reflectors larger than twenty meters in diameter. Good compression performance and reliability can be achieved by employing rigidisable inflatable tubes. The concept presented in this paper will focus on the development and simulation of a one meter diameter hexagonal reflector substructure that can be easily expanded to larger diameters due to its modular design. The one meter diameter modular approach was chosen to be able to build a full size benchmark model to validate the numerical data in the future. Due to the fact that the tensegrity compression elements are not initiating at one specific location, a passive reaction gas inflation technique is proposed which makes the structure independent of any pumps or other active inflation devices. This paper will discuss the use of inflatable rigidizable elements and their counteraction with the rest of the tensegrity structure. Simulations have been undertaken to capture the deployment behaviour of the inflating tube while getting perturbated by the attached tensegrity tension cables. These simulations showed that the use of inflatable rigidisable struts in tensegrity assemblies can greatly decrease the system mass and stowed volume, especially for very large reflectors compared to conventional approaches

Impact of 3D IC on NoC Topologies: A Wire Delay Consideration

International audienceIn this paper, we perform an exploration of 3D NoC architectures through physical design implementation based on two tiers Tezzaron 3D technology. The 3D NoC partitioning is done by dividing the NoC's datapath component into two blocks placed in the two tiers. Two Stacked NoC architectures namely Stacked 3D-Mesh NoC and Stacked 2D-Hexagonal NoC developed based on this partitioning strategy are analyzed by comparing their performances with Stacked 2D-Mesh NoC and classical 2D- Mesh and 3D-Mesh NoC. In order to measure the impact of wire delay on performance, two technology libraries (130 nm and 45 nm) representing old and advanced technologies have been used for the performance analysis. Results from physical implementations show that in advanced technologies such as 45 nm and below, the performance of Stacked 2D NoC topologies with datapath partitioning method have better performances compared with traditional 2D/3D Mesh topologies and Stacked 3D Mesh topology. We advocate here that with stacking there is no need for 3D NoC topologies for advanced 2-tier 3D IC and this is also confirmed for multistage networks like butterfly