A Framework for Verification of Signal Propagation Through Sequential Nanomagnet Logic Devices

Nanomagnet Logic is an emerging technology for low-power, highly-scalable implementation of quantum-dot cellular automata. Feedback permits reuse of logical subroutines, which is a desired functionality of any computational device. Determining whether feedback is feasible is essential to assessing the robustness of nanomagnet logic in any pipelined computing design. Therefore, development of a quantitative approach for verification of feedback paths is critical for development of design and synthesis tools for nanomagnet logic structures. In this paper, a framework for verification of sequential nanomagnet logic devices is presented. A set of definitions for canonical alignment and state definitions for NML paths are presented, as well as mathematical operations for determining the resulting states. The simulation results are presented for quantification of the NML magnetization angles for horizontal, vertical, negative-diagonal, and positive diagonal geometric alignments. The presented framework may be used as the basis for defining a representation of signal propagation for design and verification for robust NML devices and preventing deadlock resulting from improper implementation

IDPAL - Input Decoupled Partially Adiabatic Logic: Implementation and Examination

This thesis presents the experimental results of a four-phase IDPAL eight-input exclusive-OR gate. The following problems with IDPAL are addressed: multistage circuits malfunctioning, simulation convergence anomalies, and inferring input information through the power clock current. EPAD MOSFETs, which provide a low threshold voltage, are shown to be unsuccessful in correcting the malfunctioning behavior of multilayer circuits. A solution to multilayer IDPAL circuits malfunctioning, called IDPAL with discharge, is shown. The differences between simulation waveforms produced by LTspice and the experimental circuits recorded by a Tektronix’s Oscilloscope are investigated. IDPAL is implemented and analyzed using ALD MOSFETs for the following adiabatic families: 2N-2P, IDPAL, and IDPAL with discharge