Code Scheduling for Multiple Instruction Stream Architectures

Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents our investigation into ways to modify MIMD architectures to allow them to extract the instruction level parallelism achieved by current superscalar and VLIW machines. A new architecture is proposed which utilizes the advantages of a multiple instruction stream design while addressing some of the limitations that have prevented MIMD architectures from performing ILP operation. A new code scheduling mechanism is described to support this new architecture by partitioning instructions across multiple processing elements in order to exploit this level of parallelism. 1. Introduction The compiler and code scheduler for a multi-issue architecture requires a high degree of sophistication in order to realize the full potential for parallel execution. It must be able to assign independent instructions to operational units in a manner that minimizes the number of cycles in w..