1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis

We present a 64-channel cross-correlator system for space-borne synthetic aperture imaging. Two different types of ASICs were developed to fit into this system: An 8-channel comparator ASIC implemented in a 130 nm SiGe BiCMOS process technology performs A/D conversion, while a single 64-channel digital cross-correlator ASIC implemented in a 65 nm CMOS process performs the signal processing. The digital ASIC handles 2016 cross-correlations at up to 3.6 GS/s and has a power dissipation of only 0.13 mW/correlation/GHz at a supply voltage of 1 V. The comparator ASIC can handle sample rates of at least 4.5 GS/s with a power dissipation of 47 mW/channel or 1 GS/s with a power dissipation of 17 mW/channel. The assembled system consists of a single board measuring a mere 136 x 136 mm(2) and weighing only 135 g. The assembled system demonstrates crosstalk of 0.04% between neighboring channels and stability of 800 s. We provide ASIC and system-board measurement results that demonstrate that aperture synthesis can be a viable approach for Earth observation from a geostationary Earth orbit

Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models

Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. Any device that can reduce the load on, for example, a PC’s processor, is advantageous. Hence we present FPGA implementations of the decoder based alternately on discrete and continuous hidden Markov models (HMMs) representing monophones, and demonstrate that the discrete version can process speech nearly 5,000 times real time, using just 12% of the slices of a Xilinx Virtex XCV1000, but with a lower recognition rate than the continuous implementation, which is 75 times faster than real time, and occupies 45% of the same device

BDAQ53, a versatile pixel detector readout and test system for the ATLAS and CMS HL-LHC upgrades

BDAQ53 is a readout system and verification framework for hybrid pixel detector readout chips of the RD53 family. These chips are designed for the upgrade of the inner tracking detectors of the ATLAS and CMS experiments. BDAQ53 is used in applications where versatility and rapid customization are required, such as in laboratory testing environments, test beam campaigns, and permanent setups for quality control measurements. It consists of custom and commercial hardware, a Python-based software framework, and FPGA firmware. BDAQ53 is developed as open source software with both software and firmware being hosted in a public repository.Comment: 6 pages, 6 figure