Clock Tree Synthesis For Multi-Chip Modules

While designing interconnect for MCM's, one must take into consideration the distributed RLC e#ects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCM's. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for bu#er insertion to satisfy constraints on the clock signal slew rate. Experimental results, veri#ed by SPICE simulations, show that this methodcan be usedto build clock trees with near-zero skews