빠른 성능조건 만족을 위한 임계경로를 고려하는 상위 수준 합성

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 최기영.Rapid advancement of process technology enables designers to integrate various functions onto a single chip and to realize diverse requirements of customers, but productivity of system designers has improved too slowly to make optimal design in time-to-market. Since designing at higher levels of abstraction reduces the number of design instances to be considered to acquire an optimal design, it improves quality of system as well as reduces design time and cost. High-level synthesis, which maps behavioral description models to register-transfer models, can improve design productivity drastically, and thus, it has been one of the important issues in electronic system level design. Centralized controllers commonly used in high-level synthesis often require long wires and cause high load capacitance, and that is why critical paths typically occur on paths from controllers to data registers instead of paths from data registers to data registers. However, conventional high-level synthesis has focused on delays within a datapath, making it difficult to solve the timing closure problem during physical synthesis. This thesis presents hardware architecture with a distributed controller, which makes the timing closure problem much easier. A novel critical-path-aware high-level synthesis flow is also presented for synthesizing such hardware through datapath partitioning, register binding, and controller optimization. We explore the design space related to the number of partitions, which is an important design parameter for target architecture. According to our experiments, the proposed approach reduces the critical path delay excluding FUs by 29.3% and that including FUs by 10.0%, with 2.2% area overhead on average compared to centralized controller architecture. We also propose two approaches, clock gating and register constrained flow, to alleviate high peak current problem which is caused by the proposed approach. These approaches suppress the peak current overhead to keep it less than 3.6%.Chapter 1 Introduction 1 Chapter 2 Background 7 2.1 High-level Synthesis 7 2.2 Subtasks of High-level Synthesis 8 2.2.1 Operation Scheduling and FU Binding 8 2.2.2 Register Binding 10 2.2.3 Controller Synthesis 11 2.2.4 Functional Pipelining Technique for High-level Synthesis 11 2.3 Centralized Controller Architecture 12 2.4 Design Closure Problem in High-level Synthesis 15 2.5 Thesis Contribution 18 Chapter 3 Target Architecture and Overall flow 21 3.1 Target Architecture 21 3.2 Overall flow 23 Chapter 4 Critical-Path-Aware Datapath Partitioning 27 4.1 Introduction 27 4.2 Problem Formulation 30 4.3 Proposed Algorithm 32 4.4 Exploring Design Space for the Number of Partitions 36 Chapter 5 Critical-Path-Aware Register Binding 39 5.1 Introduction 39 5.2 Problem Formulation 40 5.3 Proposed Algorithm 43 Chapter 6 Critical-Path-Aware Controller Optimization 49 6.1 Introduction 49 6.2 Problem Formulation 50 6.3 Proposed Algorithm 55 Chapter 7 Evaluation 63 7.1 Experimental Setup 63 7.2 Design Parameters and Computation Time 66 7.3 Analysis Critical Path Delay on Distributed Controller Architecture 68 7.4 Analysis of Performance and Area 70 7.5 Energy Consumption 78 7.6 Analysis on Register Overhead 80 7.6.1 Clock Gating Approach 81 7.6.2 Register Constrained Approach 84 7.6.3 Combined Approach 86 7.7 Join to Conventional Optimization Techniques on HLS 87 7.8 Comparison with DRFM Binding Approach 87 Chapter 8 Conclusion and Future Work 89 8.1 Summary 89 8.2 Future Work 90 Bibliography 93 Abstract in Korean 103Docto

Clock period optimization during resource sharing and assignment

Abstract- This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. We focus on behavioral specifications with mutually exclusive paths, due to the presence of nested conditional branches and loops. It is shown that even when the set of available resources is fixed, different assignments may lead to circuits with significant differences in clock period. We provide a comprehensive analysis of how resource sharing and assignment introduces long paths in the circuit. Based on the analysis, we develop an assignment algorithm which uses a high-level delay estimator to assign operations to a fixed set of available resources so as to minimize the clock period of the resultant circuit. Experimental results on several conditionalintensive designs demonstrate the effectiveness of the assignment algorithm. I