Characterizing noise pulse effects on the power consumption of idle digital cells

The occurrence of voltage noise in digital circuits has been typically associated to logic errors. The noise exposure of nano-scale circuits, associated to process variability, makes it interesting to explore the impact of input noise voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised. This work proposes a simple yet effective characterization model to characterize the resulting shift in static energy consumption. The characterization scheme allows a fast calculation of the statistical distribution of the energy shift in digital cells affected by random noise pulses, also considering process variations. The accuracy of the approach has been tested against SPICE simulation, reaching 104 speedup in calculation run time