Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

Electrodeposition of manganese/cobalt alloys for solid oxide fuel cell interconnect applications.

With the reduction of solid oxide fuel cell (SOFC) operation temperature from 1000°C to 800°C, it is possible to use stainless steel as interconnect. Chromia forming ferritic stainless steels are the most acceptable materials for interconnects application because of their cost effectiveness and good oxidation resistance, as compared to other candidates. However, excessive scale growth and chromium evaporation will degrade the cell performance rapidly. Highly conductive coatings that aide oxidation resistance and prevent chromium evaporation may prevent the problems. (Mn,Co)3O4 spinel is one of the most promising coatings for interconnect application on account of its high conductivity, good chromium retention capability, as well as good CTE match with fuel cell materials. The traditional deposition methods, slurry coating and physical vapor deposition, have been carried out for the interconnect application. However, these methods have several limitations. Electrodeposition of thin film metallic layers followed by controlled oxidation to achieve the desired spinel phase offers an additional deposition option that is both cost effective and adaptable to work piece geometry. This work presents binary Mn/Co alloys deposition by DC and pulse plating. The dramatic difference of deposition potentials of Mn (−1.18V) and Co (−0.28V) makes it quite difficult to co-deposit two metals. Potentiodynamic polarization and cyclic voltammetry were conducted to characterize total reactions occurring during deposition. Effects of current density and pulse cycle on the surface morphologies and compositions of coatings were studied. Mn content increases with the on-time increasing, and surface morphologies changes from flake like structure to crystalline structures with less pores. Area specific resistance (ASR) measurement is used to characterize the conductivity of the coating. In tests of 1200 h, ASR is quite stable with a slight increase. The ASR value at 40,000h was predicted to be 0.0460 Ω cm2, which is well below the industry accepted goal of 0.1 Ω cm2. Following and interconnect on-cell tests have substantiated that the coating by electrodeposition can successfully block chromium evaporation, maintain high conductivity and survive thermal cycles. Therefore, this simple and cost effective coating technique is a great option for SOFC interconnects. Furthermore, in-situ mass gain of deposition can be monitored by quartz crystal microbalance (QCM). As expected, little mass gain was found for pure Mn deposition due to its high chemical reactivity. Combined with electrochemical calculations, Mn reaction with water is found to be the largest barrier for Mn electrodeposition. Several suggestions were recommended for future studies

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

Power distribution network inductance calculation, transient current measurement and conductor surface roughness extraction

The first part in the thesis discussed the modeling of the mid-frequency inductance for Zpp type plane pairs in power distribution networks (PDN). It is a key step for the placement of the decoupling capacitors. This paper gives an efficient approach for the calculation of the inductance for different capacitor placements. The PEEC based formulations takes advantage of the opposite currents in the planes. This leads to compute time reductions and memory savings for both the element calculation and the matrix solve step. A formulation is used where placement of capacitors leads to only small changes in the circuit matrix. Comparisons with other models are made to validate our results. In the second part, the application of GMI probe to measure IC switching current. IC switching current is the main noise source of many power integrity issues in printed circuit boards. Accurate measurement of the current waveforms is critical for an effective power distribution network design. In this paper, using a giant magneto-impedance (GMI) probe for this purpose is studied. A side-band detection and demodulation system is built up to measure various time-domain waveforms using an oscilloscope. It is found that the GMI probes are potentially suitable for this kind of time-domain measurements, but probe designs and measurement setups need further improvements for this application. In the third part, the new Sigma rule to evaluate parameters of copper surface roughness in PCB layers is presented. This approach is based on taking SEM images of PCB cross-sections. The approach is automat [sic] zed [sic] by applying image processing tools and Matlab code to evaluate average roughness amplitude and period of roughness function. This information could be used in numerical and analytical modeling, as well as in the DERM method to separate rough conductor loss from dielectric loss --Abstract, page iv

Designing Thermal Modulators for Portable GC x GC Systems.

Microelectromechanical systems (MEMS) have the advantage of scale and can be manufactured in bulk. One of the active areas of MEMS research is the development of micro-scale comprehensive two-dimensional gas chromatography (μGC×μGC). Our previous work demonstrated the development of the first microscale thermal modulator(µTM) for use in GC×GC. However, our demonstration was limited to very simple mixtures. Rapid, GC×GC separations by use of a mid-point µTM are demonstrated and the effects of various µTM design and operating parameters on performance are characterized here. A 9 compound structured chromatogram and a 21-component separation was achieved in < 3 min. Next we demonstrate GC × GC with all microfabricated components. The first dimension consists of two series coupled μcolumn chips with etched channels, with a PDMS stationary phase. The second dimension consists of a μcolumn chip with either a trigonal tricationic room-temperature ionic liquid (RTIL) or a commercial poly(trifluoropropylmethyl siloxane) (OV-215) stationary phase. Conventional injection methods and flame ionization detection were used. Current conventional thermal modulators can achieve FWHH of modulated peaks of ~ 10 ms, which is necessary to obtain optimum peak capacity in GC×GC by using cryogenic consumables or high amounts of power. However, since we are limited in the amount of cooling power we can use, we need to understand the fundamental physics governing the thermal modulation, and optimize our modulators. Hence we developed a theoretical model of single-stage TM with the aim to elucidate factors leading to improvements in GC×GC analyses. Model predictions were compared with experimental data obtained using our μTM operating as a single-stage TM and excellent match is obtained. To make a more realistic model, we demonstrated the physics behind the operation of a two-stage modulator. We show that parameters such as the time constant of modulation can be used to reduce the FWHH, breakthrough and hence improve the peak capacity of the GC×GC significantly. Going forward, this theory can be used to optimize the performance of the thermal modulator and coupled with thermal simulations to design the next generation of thermal modulators.PhDMechanical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116744/1/dibya_1.pd

Delay line based passive radio frequency identification tags

This work describes the concept, design, fabrication, and characterization of delay-based radio frequency identification (RFID) tags and RFID-based sensor tags, representing a novel RFID technology. The presented delay-based RFID concept is based on the LC-delay-line and transmission-delay-line based approaches. The proposed concept allows the realization of RFIDs and RFID-based sensor tags at any allowed radio frequency, with the limitation of realizing delay elements capable of producing required delays. The RFID configurations presented in this work are for operation at 915 MHz. Simulations are used to design and optimize components and devices that constitute the tags, and to integrate them to realize tags of different configuration. A set of fabrication processes has been developed for the realization of the tag. Characterization and field testing of these tags show that delay-based RFID approach can be used to make passive tags at ultra high frequency (UHF) and other allowed frequencies. Delay-based tags have the advantages of time domain operation, and the feasibility of complying with FCC regulations. However, size, need of isolators and circulator, and design constraints in producing higher number of bits are some of the concerns that need to be further addressed. In summary, this dissertation work presents a viable alternative RFID approach based on the delay line concept. The results obtained show great promise for further development and optimization of this approach for a wide range of commercial applications

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Broadcast-oriented wireless network-on-chip : fundamentals and feasibility

Premi extraordinari doctorat UPC curs 2015-2016, àmbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una àmplia adopció dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operació coordinada de múltiples nuclis de procés. Generacions successives han anat integrant més nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuï, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexió és un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un tràfic eminentment variable i heterogeni dels processadors amb molts nuclis. Són necessàries solucions ràpides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situació que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'ús d'arquitectures i models de programació lents, ineficients o poc programables. L'aparició de noves tecnologies d'interconnexió ha possibilitat la creació de NoCs més flexibles i escalables. En particular, la comunicació intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb tràfic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant múltiples canals sense fils per interconnectar nuclis allunyats entre sí. Aquesta estratègia és efectiva per complementar a NoCs clàssiques en escales mitjanes, però és probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales més grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al màxim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visió més àmplia on un BoWNoC serviria tràfic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades més pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball té com a objectius no només estudiar els aspectes fonamentals del paradigma BoWNoC, sinó també demostrar la seva viabilitat des dels punts de vista de la implementació, i del disseny de xarxa i arquitectura. Una exploració a la capa física valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'ús d'antenes de grafè a la banda dels terahertz ja a més llarg termini. A capa d'enllaç, la tesi aporta una anàlisi del context de l'aplicació que és, més tard, utilitzada per al disseny d'un protocol d'accés al medi que permet servir tràfic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visió híbrida és avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfície de xarxa, mostrant grans millores de rendiment per una àmplia selecció de patrons de tràfic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no només és debatut de forma qualitativa i genèrica, sinó també avaluat quantitativament per una arquitectura concreta enfocada a la sincronització. Els resultats demostren que l'impacte de BoWNoC pot anar més enllà d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version