INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

CMOS IMAGE SENSORS FOR LAB-ON-A-CHIP MICROSYSTEM DESIGN

The work described herein serves as a foundation for the development of CMOS imaging in lab-on-a-chip microsystems. Lab-on-a-chip (LOC) systems attempt to emulate the functionality of a cell biology lab by incorporating multiple sensing modalidites into a single microscale system. LOC are applicable to drug development, implantable sensors, cell-based bio-chemical detectors and radiation detectors. The common theme across these systems is achieving performance under severe resource constraints including noise, bandwidth, power and size. The contributions of this work are in the areas of two core lab-on-a-chip imaging functions: object detection and optical measurements

DESIGN OF A BURST MODE ULTRA HIGH-SPEED LOW-NOISE CMOS IMAGE SENSOR

Ultra-high-speed (UHS) image sensors are of interest for studying fast scientific phenomena and may also be useful in medicine. Several published studies have recently achieved frame rates of up to millions of frames per second (Mfps) using advanced processes and/or customized processes. This thesis presents a burst-mode (108 frames) UHS low-noise CMOS image sensor (CIS) based on charge-sweep transfer gates in an unmodified, standard 180 nm front-side-illuminated CIS process. By optimizing the photodiode geometry, the 52.8 μm pitch pixels with 20x20 μm^2 of active area, achieve a charge-transfer time of less than 10 ns. A proof-of-concept CIS was designed and fabricated. Through characterization, it is shown that the designed CIS has the potential to achieve 20 Mfps with an input-referred noise of 5.1 e− rms

Generic radiation hardened photodiode layouts for deep submicron CMOS image sensor processes

Selected radiation hardened photodiode layouts, manufactured in a deep submicron CMOS Image Sensor technology, are irradiated by 60Co gamma-rays up to 2.2 Mrad(SiO2) and studied in order to identify the most efficient structures and the guidelines (recess distance, bias voltage) to follow to make them work efficiently in such technology. To do so, both photodiode arrays and active pixel sensors are used. After 2.2 Mrad(SiO2), the studied sensors are fully functional and most of the radiation hardened photodiodes exhibit radiation induced dark current values more than one order of magnitude lower than the standard photodiode

A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process

A sub-0.5e−rms temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18μm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5μm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5μA the sensor chip features an input-referred noise histogram from 0.25 e−rms to a few e−rms peaking at 0.48 e−rms. The imager features a full well capacity of 6400 e− and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6e-/s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode

MOSFET Modulated Dual Conversion Gain CMOS Image Sensors

In recent years, vision systems based on CMOS image sensors have acquired significant ground over those based on charge-coupled devices (CCD). The main advantages of CMOS image sensors are their high level of integration, random accessibility, and low-voltage, low-power operation. Previously proposed high dynamic range enhancement schemes focused mainly on extending the sensor dynamic range at the high illumination end. Sensor dynamic range extension at the low illumination end has not been addressed. Since most applications require low-noise, high-sensitivity, characteristics for imaging of the dark region as well as dynamic range expansion to the bright region, the availability of a low-noise, high-sensitivity pixel device is particularly important. In this dissertation, a dual-conversion-gain (DCG) pixel architecture was proposed; this architecture increases the signal to noise ratio (SNR) and the dynamic range of CMOS image sensors at both the low and high illumination ends. The dual conversion gain pixel improves the dynamic range by changing the conversion gain based on the illumination level without increasing artifacts or increasing the imaging readout noise floor. A MOSFET is used to modulate the capacitance of the charge sensing node. Under high light illumination conditions, a low conversion gain is used to achieve higher full well capacity and wider dynamic range. Under low light conditions, a high conversion gain is enabled to lower the readout noise and achieve excellent low light performance. A sensor prototype using the new pixel architecture with 5.6μm pixel pitch was designed and fabricated using Micron Technology’s 130nm 3-metal and 2-poly silicon process. The periphery circuitries were designed to readout the pixel and support the pixel characterization needs. The pixel design, readout timing, and operation voltage were optimized. A detail sensor characterization was performed; a 127μV/e was achieved for the high conversion gain mode and 30.8μV/e for the low conversion gain mode. Characterization results confirm that a 42ke linear full well was achieved for the low conversion gain mode and 10.5ke for the high conversion gain mode. An average 2.1e readout noise was measured for the high conversion gain mode and 8.6e for the low conversion gain mode. The total sensor dynamic range was extended to 86dB by combining the two modes of operation with a 46.2dB maximum SNR. Several images were taken by the prototype sensor under different illumination levels. The simple processed color images show the clear advantage of the high conversion gain mode for the low light imaging

A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode

Design and characterization of ultra high frame rate burst image sensors

This thesis research was aimed at investigating and designing novel architectures required for ultra high frame rate (UHFR) imagers capable of operating at frame rates in excess of 106 frames/sec. To demonstrate the feasibility of these architectures, a 180 x 180 element UHFR-I imager was designed and fabricated. The imager chip stored the latest 32 frames at its on-chip memory locations rather than performing a continuous readout. It was demonstrated that this architecture approach could achieve a frame acquisition rate of 2 x 106 frames/sec. Additionally, other novel design features were incorporated to minimize optical cross talk and output amplifier noise, and maximize charge handling capacity. Two-dimensional (2-D) process and device simulations were performed to optimize optical cross talk and results compared favorably with experimental data of the fabricated chip. This tested imager was fabricated at the research laboratory of Sarnoff Corporation and had 4-levels of polysilicon, 3-levels of metal, eight implants and 21 photo mask levels. Simulations were also performed to characterize optical cross talk as a function of wavelength, optical shield aperture and epi-substrate doping. The measured value of optical cross talk was at least a factor of 40 times lower and maximum frame rate was a factor of 4 higher than previously published results for very high frame rate (VHFR) imager. The experimental results were used to design a new 64 x 64 element UHFR-II imager with an architecture capable of an image capture rate of 107 frames/sec. This architecture requires only 3-levels of polysilicon and 2-levels of metal and stores the latest 12 frames at its on-chip memory locations. Simulation results indicate that a frame rate of 107 frames/sec can certainly be obtained

Modelling and characterization of small photosensors in advanced CMOS technologies

The rapid scaling of CMOS technologies and the development of optimized CIS (CMOS Image Sensor) processes for CMOS vision products has not been met by a similar effort in a comprehensive study of the main physical phenomena dominating the behavior of pixels at these technological nodes. This work provides a study of the behaviour of small photodetectors in advanced CMOS technologies in order to evaluate the impact of the geometry on the pixel photoresponse. Several models were developed paying special attention to the peripheral collection. The results suggest that the largest active area no longer necessarily guarantees the optimum response and show the significance of the lateral contribution for small photodiodes. That is, they establish the need to find a trade-off between the active area and the collecting area surrounding the junction to maximize the response. Based on the solution of the two-dimensional steady-state equation in the surroundings of the junction, an analytical model for uniformly illuminated p-n+ junction photodiodes was proposed. It is compact, general and scalable. In order to be used in Computer Aided Design (CAD) tools, the model was implemented in a Hardware Description Language (HDL) and used for circuit simulations to illustrate the potential of the model for the optimization of the pixel performance

Circuits and Systems for Lateral Flow Immunoassay Biosensors at the Point-of-Care

Lateral Flow Immunoassays (LFIAs) are biosensors, which among others are used for the detection of infectious diseases. Due to their numerous advantages, they are particularly suitable for point of care testing, especially in developing countries where there is lack of medical healthcare centers and trained personnel. When the testing sample is positive, the LFIAs generate a color test line to indicate the presence of analyte. The intensity of the test line relates to the concentration of analyte. Even though the color test line can be visually observed for the accurate quantification of the results in LFIAs an external electronic reader is required. Existing readers are not fully optimized for point-of-care (POC) testing and therefore have significant limitations. This thesis presents the development of three readout systems that quantify the results of LFIAs. The first system was implemented as a proof of concept of the proposed method, which is based on the scanning approach without using any moving components or any extra optical accessories. Instead, the test line and the area around it, are scanned using an array of photodiodes (1 × 128). The small size of the pixels gives the system sufficient spatial resolution, to avoid errors due to positioning displacement of the strip. The system was tested with influenza A nucleoprotein and the results demonstrate its quantification capabilities. The second generation system is an optimized version of the proof of concept system. Optimization was performed in terms of matching the photodetectors wavelength with the maximum absorption wavelength of the gold nanoparticles presented in the tested LFIA. Ray trace simulations defined the optimum position of all the components in order to achieve uniform light distribution across the LFIA with the minimum number of light sources. An experimental model of the optical profile of the surface of LFIA was also generated for accurate simulations. Tests of the developed system with LFIAs showed its ability to quantify the results while having reduced power consumption and better limit of detection compared to the first system. Finally, a third generation system was realized which demonstrated the capability of having a miniaturized reader. The photodetector of the previous systems was replaced with a CMOS Image Sensor (CIS), specifically designed for this application. The pixel design was optimized for very low power consumption via biasing the transistors in subthreshold and by reusing the same amplifier for both photocurrent to voltage conversion and noise cancellation. With uniform light distribution at 525 nm and 76 frames/s the chip has 1.9 mVrms total output referred noise and a total power consumption of 21 μW. In tests with lateral flow immunoassay, this system detected concentrations of influenza A nucleoprotein from 0.5 ng/mL to 200 ng/mL