Low Power, Area Efficient Architecture for Successive Cancellation Decoder

Polar codes have recently emerged as an error-correcting code and have become popular owing to their capacity-achieving nature. Polar code based communication system primarily consists of two parts, including Polar Encoder and Decoder. Successive Cancellation Decoder is one of the methods used in the decoding process. The Successive Cancellation Decoder is a recursive structure built with the building block called Processing Element. This article proposes a low power, area-efficient architecture for the Successive Cancellation Decoder for polar codes. Successive Cancellation Decoder with code length 1024 and code rate 0.5 was designed in Verilog HDL and implemented using 45-nm CMOS technology. The proposed work focuses on developing an area-efficient Successive Cancellation Decoder architecture by presenting a new Processing Element architecture. The proposed architecture has produced about 35% lesser area with a 12% reduced gate count. Moreover, power is also reduced by 50%. A substantial reduction in the latency and improvement in the Technology Scaled Normalized Throughput value was observed

An improved algorithm of generating shortening patterns for polar codes

The rate matching in polar codes becomes a solution when non-conventional codewords of length N≠2n are required. Shortening is employed to design arbitrary rate codes from a mother code with a given rate. Based on the conventional shortening scheme, length of constructed polar codes is limited. In this paper, we demonstrate the presence of favorable and unfavorable shortening patterns. The structure of polar codes is leveraged to eliminate unfavorable shortening patterns, thereby reducing the search space. We generate an auxiliary matrix through likelihood and subsequently select the shortening bits from the matrix. Unlike different existing methods that offer only a single shortening pattern, our algorithm generates multiple favorable shortening patterns, encompassing all possible favorable configurations. This algorithm has a reduced complexity and suboptimal performance, effectively identifying shortening patterns and sets of frozen symbols for any polar code. Simulation results underscore that the shortened polar codes exhibit performance closely aligned with the mother codes. Our algorithm addresses this security concern by making it more difficult for an attacker to obtain the information set and frozen symbols of a polar code. This is done by generating multiple shortening patterns for any polar code

A New Coding Paradigm for the Primitive Relay Channel

We consider the primitive relay channel, where the source sends a message to the relay and to the destination, and the relay helps the communication by transmitting an additional message to the destination via a separate channel. Two well-known coding techniques have been introduced for this setting: decode-and-forward and compress-and-forward. In decode-and-forward, the relay completely decodes the message and sends some information to the destination; in compress-and-forward, the relay does not decode, and it sends a compressed version of the received signal to the destination using Wyner-Ziv coding. In this paper, we present a novel coding paradigm that provides an improved achievable rate for the primitive relay channel. The idea is to combine compress-and-forward and decode-and-forward via a chaining construction. We transmit over pairs of blocks: in the first block, we use compress-and-forward; and in the second block, we use decode-and-forward. More specifically, in the first block, the relay does not decode, it compresses the received signal via Wyner-Ziv, and it sends only part of the compression to the destination. In the second block, the relay completely decodes the message, it sends some information to the destination, and it also sends the remaining part of the compression coming from the first block. By doing so, we are able to strictly outperform both compress-and-forward and decode-and-forward. Note that the proposed coding scheme can be implemented with polar codes. As such, it has the typical attractive properties of polar coding schemes, namely, quasi-linear encoding and decoding complexity, and error probability that decays at super-polynomial speed. As a running example, we take into account the special case of the erasure relay channel, and we provide a comparison between the rates achievable by our proposed scheme and the existing upper and lower bounds.Comment: 10 pages, 4 figures, in Proc. of ISIT'18 (short version) and in Algorithms (full version

System Development and VLSI Implementation of High Throughput and Hardware Efficient Polar Code Decoder

Polar code is the first channel code which is provable to achieve the Shannon capacity. Additionally, it has a very good performance in terms of low error floor. All these merits make it a potential candidate for the future standard of wireless communication or storage system. Polar code is received increasing research interest these years. However, the hardware implementation of hardware decoder still has not meet the expectation of practical applications, no matter from neither throughput aspect nor hardware efficient aspect. This dissertation presents several system development approaches and hardware structures for three widely known decoding algorithms. These algorithms are successive cancellation (SC), list successive cancellation (LSC) and belief propagation (BP). All the efforts are in order to maximize the throughput meanwhile minimize the hardware cost. Throughput centric successive cancellation (TCSC) decoder is proposed for SC decoding. By introducing the concept of constituent code, the decoding latency is significantly reduced with a negligible decoding performance loss. However, the specifically designed computation unites dramatically increase the hardware cost, and how to handle the conventional polar code sets and constituent codes sets makes the hardware implementation more complicated. By exploiting the natural property of conventional SC decoder, datapaths for decoding constituent codes are compatibly built via computation units sharing technique. This approach does not incur additional hardware cost expect some multiplexer logic, but can significantly increase the decoding throughput. Other techniques such as pre-computing and gate-level optimization are used as well in order to further increase the decoding throughput. A specific designed partial sum generator (PSG) is also investigated in this dissertation. This PSG is hardware efficient and timing compatible with proposed TCSC decoder. Additionally, a polar code construction scheme with constituent codes optimization is also presents. This construction scheme aims to reduce the constituent codes based SC decoding latency. Results show that, compared with the state-of-art decoder, TCSC can achieve at least 60% latency reduction for the codes with length n = 1024. By using Nangate FreePDK 45nm process, TCSC decoder can reach throughput up to 5.81 Gbps and 2.01 Gbps for (1024, 870) and (1024, 512) polar code, respectively. Besides, with the proposed construction scheme, the TCSC decoder generally is able to further achieve at least around 20% latency deduction with an negligible gain loss. Overlapped List Successive Cancellation (OLSC) is proposed for LSC decoding as a design approach. LSC decoding has a better performance than LS decoding at the cost of hardware consumption. With such approach, the l (l > 1) instances of successive cancellation (SC) decoder for LSC with list size l can be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. Meanwhile, approaches to reduce the latency associated with the pipeline scheme are also investigated. Simulation results show that with proposed design approach the hardware efficiency is increased significantly over the recently proposed LSC decoders. Express Journey Belief Propagation (XJBP) is proposed for BP decoding. This idea origins from extending the constituent codes concept from SC to BP decoding. Express journey refers to the datapath of specific constituent codes in the factor graph, which accelerates the belief information propagation speed. The XJBP decoder is able to achieve 40.6% computational complexity reduction with the conventional BP decoding. This enables an energy efficient hardware implementation. In summary, all the efforts to optimize the polar code decoder are presented in this dissertation, supported by the careful analysis, precise description, extensively numerical simulations, thoughtful discussion and RTL implementation on VLSI design platforms