Cell Architecture for Nanoelectronic Design

Nanoarchitectures, fault-tolerance, defect-tolerance, noise-tolerance, averaging cellSeveral nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build medium/large systems. Nanoarchitecture proposals only solve a small part of the problems needed to achieve a real design. In this paper, we propose and analyze a cell architecture that overcomes most of those at the gate level. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure’s tolerance by taking advantage of interferences among nanodevices. Using this improvement we show that it is possible to reduce the output standard deviation by a factor larger than \u81ãN and restitute the signal levels using nanodevices

Can Large Fanin Circuits Perform Reliable Computations in the Presence of Faults?

For ordinary circuits with a fixed upper bound on the fanin of its gates it has been shown that logarithmic redundancy is necessary and sufficient to overcome random hardware faults (noise). Here, we consider the same question for unbounded fanin circuits which in the fault-free case can compute Boolean functions in sublogarithmic depth. Now the details of the fault model become more important. One may assume that only gates, resp. only wires may deliver wrong values, or that both gates and wires may behave faulty. The fault tolerance depends on the types of gates that are used, and whether the error probabilities are known exactly or only an upper bound for them. Concerning the first distinction the two most important models are circuits consisting of and- and or-gates with arbitrarily many inputs, and circuits built from the more general type of threshold gates. We will show that in case of faulty and/or--circuits as well as threshold circuits an increase of fanin and size cannot be ..