Calibration Setup for Ultralow-Current Transresistance Amplifiers

We describe a setup for the calibration of the transresistance gain of low-current amplifiers, based on the capacitance-charging method. The calibration can be performed in the current range of typical interest for electron-counting experiments. The setup implementation is simple and rugged, and is suitable to be embedded in larger experiments, where the amplifier is employed. The calibrated transresistance is traceable to the units of capacitance and time. Two different calibration modes were tested: with dc current (obtained using a custom-made piecewise linear ramp generator) and with low-frequency sinewave current (using a commercial generator). The relative base accuracy of the implementation is in the 10⁻⁵ range

Comparison of Low DC Current Traceability Methods and Gas Capacitors AC–DC Dependence

partially_open6sìThis article compares two instruments for the traceable measurement of dc low currents, a custom capacitance-voltage (C-V) source and the ultrastable low-current amplifier (ULCA), a commercial precision transresistance amplifier. The instruments are calibrated through independent traceability routes. The comparison base relative accuracy is in the 10(-6)-10(-5) range. Differences between the two instrument readings, in the 10(-5) range, are interpreted as an effect of the frequency dependence of the capacitor employed in the C-Vsource. Such frequency dependence can also affect primary metrology experiments in other fields.openCallegaro, Luca; Cassiago, Cristina; D'Elia, Vincenzo; Gasparotto, Enrico; Enrico, Emanuele; Gotz, MartinCallegaro, Luca; Cassiago, Cristina; D'Elia, Vincenzo; Gasparotto, Enrico; Enrico, Emanuele; Gotz, Marti

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl

Development of frequency division multiplexing readout for a large transition edge sensor array for space

The light in sub-millimeter and far-Infrared (FIR) wavelengths from deep space can travel in an incredibly long distance and contains rich, unique information, which can help astronomers to reveal the history of the universe and answer outstanding questions such as the origin of galaxies, stars, and planets. Sensitive transition edge sensor (TES) bolometers in combination with frequency division multiplexing (FDM) readout system that can read out multiple pixels simultaneously are the candidate detector technology for several space missions operated at sub-millimeter and FIR wavelengths. My thesis reports the study and development of an FDM-readout system for TES bolometers, containing five main scientific sub-projects focusing on building systematically a readout demonstration system. Characterizing the noise of the readout system is essential. Chapter 3 and 4 report studies of the noise from room- and cryogenic-temperature electrical components, respectively. Chapter 5 presents a map of all pixels in the FDM-system, aiming to reduce the unwanted noise between pixels within a TES bolometer array. Chapter 6 demonstrates an FDM-system that can read out 60 low noise TES bolometers simultaneously. The readout noise of the FDM-system is lower than the noise of highly sensitive detectors and that the sensitivities measured when all pixels in operation are the same as what measured when only one pixel is operated. Chapter 7 shows further improved results on electrical-crosstalk performance and stability of the FDM-system compared to Chapter 6. We report a full demonstration of the FDM-system in the lab, opening the door to the readout for space observatories

Design of high speed folding and interpolating analog-to-digital converter

High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F&I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F&I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F&I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35μm CMOS process to verify the ideas. The S/H and F&I ADC prototype is realized in 0.35μm double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /