A 16-bit CORDIC rotator for high-performance wireless LAN

In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm2 and it dissipates 7 mW power at 20 MHz frequency

New virtually scaling free adaptive CORDIC rotator

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector

In this paper, we propose a CORDIC like algorithm for computing absolute magnitude of a vector and its corresponding phase angle. It eliminates scale factor compensation step as well as the addition/subtraction operation along the z datapath. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications

Design citeria for applications with non-manifest loops

In the design process of high-throughput applications, design choices concerning the type of processor architecture and appropriate scheduling mechanism, have to be made. Take a reed-solomon decoder as an example, the amount of clock cycles consumed in decoding a code is dependent on the amount of errors within that code. Since this is not known in advance, and the environment in which the code is transmitted can cause a variable amount of errors within that code, a processor architecture which employs a static scheduling scheme, has to assume the worst case amount of clock cycles in order to cope with the worst case situation and provide correct results. On the other hand a processor that employs a dynamic scheduling scheme, can gain wasted clock cycles, by scheduling the exact amount of clock cycles that are needed and not the amount of clock cycles needed for the worst case situation. Since processor architectures that employ dynamic scheduling schemes have more overhead, designers have to make their choice beforehand. In this paper we address the problem of making the correct choice of whether to use a static or dynamic scheduling scheme. The strategy is to determine whether the application possess non-manifest behavior\ud and weigh out this dynamic behavior against static scheduling solutions which were quite common in the past. We provide criteria for choosing the correct scheduling architecture for a high throughput application based upon the environmental and algorithm-specification constraints. Keywords¿ Non-manifest loop scheduling, variable latency functional units, dynamic hardware scheduling, self\ud scheduling hardware units, optimized data-flow machine architecture

A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST

A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for Wafer Scale Integration (WSI). CORDIC is designed using Transmission Gate Logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications

Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest

QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number representation system. This new representation allows performing round-tonearest at the same cost of truncation. Consequently, the rounding errors of the results are halved, which allows it to reduce the word-length by one bit. This reduction positively impacts on the area, delay and power consumption of the design.Ministry of Education and Science of Spain and Junta of Andalucía under contracts TIN2013-42253-P and TIC-1692, respectively, and Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

On the Periodic Redshifts of Galaxies and Associated QSOs

Abstract: The observed periodicity of intrinsic-redshift in galaxies and associated QSOs has been explained by using the previous theory of a gravito-cordic field for galaxies. The quantisation period is a function of the atomic fine structure constant and it depends upon an action principle operating around galactic orbits and QSOs, or between field galaxies. The calculated separations of many QSO-galaxy pairs have been found to fit a diffusion law distribution, which suggests that associated QSOs were ejected from parent galaxies. This record was migrated from the OpenDepot repository service in June, 2017 before shutting down