A efficacy of different buffer size on latency of network on chip (NoC)

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them

A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach. U7 - Cited By (since 1996): 6 U7 - Export Date: 5 February 2010 U7 - Source: Scopus U7 - Art. No.: 6843

The Dynamics of Human and Rattlesnake Conflict in Southern California

Human-rattlesnake conflict occurs when rattlesnakes are discovered in human-dominated areas and are deemed to pose an unacceptable risk to humans because of their venomous bite. In this dissertation, I investigated the nature of this conflict from the perspectives of both the behavioral and survival risks posed to rattlesnakes and the medical risks posed to humans. In the first of three studies, I investigated the effects of short- and long-distance translocation (SDT and LDT) of nuisance wildlife as a way of mitigating conflict between humans and naturally occurring Red Diamond Rattlesnakes (Crotalus ruber) near residential development in southern California. Snake activity ranges and risk of moving near human-modified areas were larger for LDT and SDT snakes than for non-translocated snakes. Snakes moved closer to human-modified areas and required translocation more often during the summer. Snakes translocated greater distances were less likely to return to human-modified areas, and translocation did not affect snake survival. In the second study, I investigated the etiology and severity of human envenomations using a retrospective review of 354 snakebite cases admitted to Loma Linda University Medical Center between 1990 and 2010. Male snakebite victims and those using alcohol or drugs were more likely to sustain bites to the upper extremity, distal to the ankle or wrist, and via illegitimate provocation of the snake. Snakebite severity was positively associated with snake size, negatively associated with patient mass, and independent of patient age, snake taxon, anatomical location of bite, legitimate versus illegitimate (provoked) bites, and time until hospital admission. Effectiveness of CroFab antivenom was similar for all southern California venomous snake taxa. In the final study, using the same medical data, I assessed the usefulness of several factors as predictors of overall snakebite severity, symptom progression, and antivenom use. Initial snakebite severity score, size of the envenoming snake, and patient mass were significant predictors. I suggested several rules of thumb that could help clinicians anticipate antivenom needs. Overall, this dissertation contributes to our understanding of the effects of mitigation translocation on rattlesnakes and the epidemiology and clinical management of venomous snakebite in southern California

Modeling Power Consumption and Temperature in TLM Models

International audienceMany techniques and tools exist to estimate the power consumption and the temperature map of a chip. These tools help the hardware designers develop power efficient chips in the presence of temperature constraints. For this task, the application can be ignored or at least abstracted by some high level scenarios; at this stage, the actual embedded software is generally not available yet. However, after the hardware is defined, the embedded software can still have a significant influence on the power consumption; i.e., two implementations of the same application can consume more or less power. Moreover, the actual software powe

European HYdropedological Data Inventory (EU-HYDI)

There is a common need for reliable hydropedological information in Europe. In the last decades research institutes, universities and government agencies have developed local, regional and national datasets containing soil physical, chemical, hydrological and taxonomic information often combined with land use and landform data. A hydrological database for western European soils was also created in the mid-1990s. However, a comprehensive European hydropedological database, with possible additional information on chemical parameters and land use is still missing. A comprehensive joint European hydropedological inventory can serve multiple purposes, including scientific research, modelling and application of models on different geographical scales. The objective of the joint effort of the participants is to establish the European Hydropedological Data Inventory (EU-HYDI). This database holds data from European soils focusing on soil physical, chemical and hydrological properties. It also contains information on geographical location, soil classification and land use/cover at the time of sampling. It was assembled with the aim of encompassing the soil variability in Europe. It contains data from 18 countries with contributions from 29 institutions. This report presents an overview of the database, details the individual contributed datasets and explains the quality assurance and harmonization process that lead to the final database

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.Las plataformas informáticas actuales fomentan la integración de miles de núcleos de procesamiento y sus interconexiones, en un solo chip. Los smartphones móviles, el IoT, los dispositivos embebidos, los ordenadores de sobremesa y los centros de datos utilizan sistemas en chip (SoC) de muchos núcleos para explotar su potencia de cálculo y paralelismo para satisfacer los requisitos de las cargas de trabajo dinámicas. Las redes en chip (NoC) conducen a una conectividad escalable para diversas aplicaciones con distintos patrones de tráfico y dependencias de datos. Sin embargo, cuando el sistema ejecuta varias aplicaciones en las NoC tradicionales -optimizadas y fijadas en el momento de síntesis, la disconformidad de la interconexión con los requisitos de las distintas aplicaciones genera limitaciones en el rendimiento. En la literatura, los diseños de NoC adoptaron la estrategia de redes definidas por software (SDN) para evolucionar hacia una solución de interconexión adaptable para los futuros chips. Sin embargo, los trabajos estudiados implementan un enfoque parcial de red definida por software en el chip (SDNoC) de SDN, dejando de lado la arquitectura en capas de SDN que aporta interoperabilidad en la red convencional. Este artículo explora la literatura sobre SDNoC y la clasifica en función de las características SDN que presenta cada trabajo. A continuación, describimos los retos y oportunidades detectados a partir del estudio de la literatura. Además, explicamos la motivación para un enfoque SDNoC, y exponemos los conceptos y arquitecturas de SDN y SDNoC. Observamos que los trabajos en la literatura emplean un enfoque SDNoC por capas no completo. Este hecho crea varias áreas fértiles en la arquitectura SDNoC en las que los investigadores pueden contribuir a los diseños de SoCs de muchos núcleos

Mechanisms of Blockade of the Muscle-Type Nicotinic Receptor by Benzocaine, a Permanently Uncharged Local Anesthetic

Most local anesthetics (LAs) are amine compounds bearing one or several phenolic rings. Many of them are protonated at physiological pH, but benzocaine (Bzc) is permanently uncharged, which is relevant because the effects of LAs on nicotinic acetylcholine (ACh) receptors (nAChRs) depend on their presence as uncharged or protonated species. The aims of this study were to assess the effects of Bzc on nAChRs and to correlate them with its binding to putative interacting sites on this receptor. nAChRs from Torpedo electroplaques were microtransplanted to Xenopus oocytes and currents elicited by ACh (IAChs), either alone or together with Bzc, were recorded at different potentials. Co-application of ACh with increasing concentrations of Bzc showed that Bzc reversibly blocked nAChRs. IACh inhibition by Bzc was voltage-independent, but the IACh rebound elicited when rinsing Bzc suggests an open-channel blockade. Besides, ACh and Bzc co-application enhanced nAChR desensitization. When Bzc was just pre-applied it also inhibited IACh, by blocking closed (resting) nAChRs. This blockade slowed down the kinetics of both the IACh activation and the recovery from blockade. The electrophysiological results indicate that Bzc effects on nAChRs are similar to those of 2,6-dimethylaniline, an analogue of the hydrophobic moiety of lidocaine. Furthermore, docking assays on models of the nAChR revealed that Bzc and DMA binding sites on nAChRs overlap fairly well. These results demonstrate that Bzc inhibits nAChRs by multiple mechanisms and contribute to better understanding both the modulation of nAChRs and how LAs elicit some of their clinical side effects.This work was supported by grants BFU2012-31359, BFU2015-66612-P, SAF2015-66275-C2-1-R and SAF2017-82977-P (AEI/FEDER, UE) from MINECO, PROMETEO/2014/11 from Generalitat Valenciana (Spain) and GRE17-01 from Universidad de Alicante. R.C. held a predoctoral fellowship from Universidad de Alicante (FPUUA36) and M.N. a predoctoral industrial fellowship from Ministerio de Economía, Industria y Competitividad (DI-16-08303)

Survey on Instruction Selection: An Extensive and Modern Literature Review

Instruction selection is one of three optimisation problems involved in the code generator backend of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation. Despite on-going research since the late 1960s, the last, comprehensive survey on the field was written more than 30 years ago. As new approaches and techniques have appeared since its publication, this brings forth a need for a new, up-to-date review of the current body of literature. This report addresses that need by performing an extensive review and categorisation of existing research. The report therefore supersedes and extends the previous surveys, and also attempts to identify where future research should be directed.Comment: Major changes: - Merged simulation chapter with macro expansion chapter - Addressed misunderstandings of several approaches - Completely rewrote many parts of the chapters; strengthened the discussion of many approaches - Revised the drawing of all trees and graphs to put the root at the top instead of at the bottom - Added appendix for listing the approaches in a table See doc for more inf

Energy analysis and optimisation techniques for automatically synthesised coprocessors

The primary outcome of this research project is the development of a methodology enabling fast automated early-stage power and energy analysis of configurable processors for system-on-chip platforms. Such capability is essential to the process of selecting energy efficient processors during design-space exploration, when potential savings are highest. This has been achieved by developing dynamic and static energy consumption models for the constituent blocks within the processors. Several optimisations have been identified, specifically targeting the most significant blocks in terms of energy consumption. Instruction encoding mechanism reduces both the energy and area requirements of the instruction cache; modifications to the multiplier unit reduce energy consumption during inactive cycles. Both techniques are demonstrated to offer substantial energy savings. The aforementioned techniques have undergone detailed evaluation and, based on the positive outcomes obtained, have been incorporated into Cascade, a system-on-chip coprocessor synthesis tool developed by Critical Blue, to provide automated analysis and optimisation of processor energy requirements. This thesis details the process of identifying and examining each method, along with the results obtained. Finally, a case study demonstrates the benefits of the developed functionality, from the perspective of someone using Cascade to automate the creation of an energy-efficient configurable processor for system-on-chip platforms