87 research outputs found
Optimization of Circuits for IBM's five-qubit Quantum Computers
IBM has made several quantum computers available to researchers around the
world via cloud services. Two architectures with five qubits, one with 16, and
one with 20 qubits are available to run experiments. The IBM architectures
implement gates from the Clifford+T gate library. However, each architecture
only implements a subset of the possible CNOT gates. In this paper, we show how
Clifford+T circuits can efficiently be mapped into the two IBM quantum
computers with 5 qubits. We further present an algorithm and a set of circuit
identities that may be used to optimize the Clifford+T circuits in terms of
gate count and number of levels. It is further shown that the optimized
circuits can considerably reduce the gate count and number of levels and thus
produce results with better fidelity
Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures
Quantum computers have recently made great strides and are on a long-term
path towards useful fault-tolerant computation. A dominant overhead in
fault-tolerant quantum computation is the production of high-fidelity encoded
qubits, called magic states, which enable reliable error-corrected computation.
We present the first detailed designs of hardware functional units that
implement space-time optimized magic-state factories for surface code
error-corrected machines. Interactions among distant qubits require surface
code braids (physical pathways on chip) which must be routed. Magic-state
factories are circuits comprised of a complex set of braids that is more
difficult to route than quantum circuits considered in previous work [1]. This
paper explores the impact of scheduling techniques, such as gate reordering and
qubit renaming, and we propose two novel mapping techniques: braid repulsion
and dipole moment braid rotation. We combine these techniques with graph
partitioning and community detection algorithms, and further introduce a
stitching algorithm for mapping subgraphs onto a physical machine. Our results
show a factor of 5.64 reduction in space-time volume compared to the best-known
previous designs for magic-state factories.Comment: 13 pages, 10 figure
Exploiting Quantum Teleportation in Quantum Circuit Mapping
Quantum computers are constantly growing in their number of qubits, but
continue to suffer from restrictions such as the limited pairs of qubits that
may interact with each other. Thus far, this problem is addressed by mapping
and moving qubits to suitable positions for the interaction (known as quantum
circuit mapping). However, this movement requires additional gates to be
incorporated into the circuit, whose number should be kept as small as possible
since each gate increases the likelihood of errors and decoherence.
State-of-the-art mapping methods utilize swapping and bridging to move the
qubits along the static paths of the coupling map---solving this problem
without exploiting all means the quantum domain has to offer. In this paper, we
propose to additionally exploit quantum teleportation as a possible
complementary method. Quantum teleportation conceptually allows to move the
state of a qubit over arbitrary long distances with constant
overhead---providing the potential of determining cheaper mappings. The
potential is demonstrated by a case study on the IBM Q Tokyo architecture which
already shows promising improvements. With the emergence of larger quantum
computing architectures, quantum teleportation will become more effective in
generating cheaper mappings.Comment: To appear in ASP-DAC 202
Full-Stack, Real-System Quantum Computer Studies: Architectural Comparisons and Design Insights
In recent years, Quantum Computing (QC) has progressed to the point where
small working prototypes are available for use. Termed Noisy Intermediate-Scale
Quantum (NISQ) computers, these prototypes are too small for large benchmarks
or even for Quantum Error Correction, but they do have sufficient resources to
run small benchmarks, particularly if compiled with optimizations to make use
of scarce qubits and limited operation counts and coherence times. QC has not
yet, however, settled on a particular preferred device implementation
technology, and indeed different NISQ prototypes implement qubits with very
different physical approaches and therefore widely-varying device and machine
characteristics.
Our work performs a full-stack, benchmark-driven hardware-software analysis
of QC systems. We evaluate QC architectural possibilities, software-visible
gates, and software optimizations to tackle fundamental design questions about
gate set choices, communication topology, the factors affecting benchmark
performance and compiler optimizations. In order to answer key cross-technology
and cross-platform design questions, our work has built the first top-to-bottom
toolflow to target different qubit device technologies, including
superconducting and trapped ion qubits which are the current QC front-runners.
We use our toolflow, TriQ, to conduct {\em real-system} measurements on 7
running QC prototypes from 3 different groups, IBM, Rigetti, and University of
Maryland. From these real-system experiences at QC's hardware-software
interface, we make observations about native and software-visible gates for
different QC technologies, communication topologies, and the value of
noise-aware compilation even on lower-noise platforms. This is the largest
cross-platform real-system QC study performed thus far; its results have the
potential to inform both QC device and compiler design going forward.Comment: Preprint of a publication in ISCA 201
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