Mismatch-induced tradeoffs and scalability of mixed-signal vision chips

This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing the power consumption, increasing the operation speed, and reducing the area occupation (i.e., increasing the density of processors), as fabrication technologies scale down into deep sub-micron.DICTAM IST- 1999-19007Comisión Interministerial de Ciencia y Tecnología TIC1999-082

CMOS Design of Focal Plane Programmable Array Processors

Abstract: While digital processors can solve problems in most application areas, in some fields their capabilities are very limited. A typical example is vision. Simple animals outperform super-computers in the realization of basic vision tasks. The limitations of conventional digital systems in this field can be overcome following a fundamentally different approach based on architectures closer to nature solutions. Retinas, the front end of biological vision systems, obtain their high processing power from parallelism, and consist of concurrent spatial distributions (on the focal plane aerea) of photoreceptors and basic analog processors with local connectivity and moderate accuracy. This can be implemented using an architecture with the following main components are: a) parallel processing through an array of locally-connected analog processors; b) a means of storing, locally, pixel-by-pixel, the intermediate computation results, and 3) stored on-chip programmability. When implemented as a mixed-signal VLSI chip, devices are obtained which are capable of image processing at rates of trillions of operations per second with very small size and low power consumption. This paper reviews the latest results on this type of chips and systems, and outlines the envisaged roadmap for these computers. 1