A Behavioral Model of a Built-in Current Sensor for IDDQ Testing

IDDQ testing is one of the most effective methods for detecting defects in integrated circuits. Higher leakage currents in more advanced semiconductor technologies have reduced the resolution of IDDQ test. One solution is to use built-in current sensors. Several sensor techniques for measuring the current based on the magnetic field or voltage drop across the supply line have been proposed. In this work, we develop a behavioral model for a built-in current sensor measuring voltage drop and use this model to better understand sensor operation, identify the effect of different parameters on sensor resolution, and suggest design modifications to improve future sensor performance

A Behavioral Model of a Built-in Current Sensor for IDDQ Testing

IDDQ testing is one of the most effective methods for detecting defects in integrated circuits. Higher leakage currents in more advanced semiconductor technologies have reduced the resolution of IDDQ test. One solution is to use built-in current sensors. Several sensor techniques for measuring the current based on the magnetic field or voltage drop across the supply line have been proposed. In this work, we develop a behavioral model for a built-in current sensor measuring voltage drop and use this model to better understand sensor operation, identify the effect of different parameters on sensor resolution, and suggest design modifications to improve future sensor performance

Voltage sensing based built-in current sensor for IDDQ test

Quiescent current leakage test of the VDD supply (IDDQ Test) has been proven an effective way to screen out defective chips in manufacturing of Integrated Circuits (IC). As technology advances, the traditional IDDQ test is facing more and more challenges. In this research, a practical built-in current sensor (BICS) is proposed and the design is verified by three generations of test chips. The BICS detects the signal by sensing the voltage drop on supply lines of the circuit under test (CUT). Then the sensor performs analog-to-digital conversion of the input signal using a stochastic process with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. This non-invasive procedure avoids any performance degradation of the CUT. The measurement results of test chips are presented. The sensor achieves a high IDDQ resolution with small chip area overhead. This will enable IDDQ of future technology generations

Integrated circuit outlier identification by multiple parameter correlation

Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed