8 research outputs found
Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions
The ever-increasing usage and application of system-on-chips (SoCs) has resulted in the tremendous modernization of these architectures. For a modern SoC design, with the inclusion of numerous complex and heterogeneous intellectual properties (IPs), and its privacy-preserving declaration, there exists a wide variety of highly sensitive assets. These assets must be protected from any unauthorized access and against a diverse set of attacks. Attacks for obtaining such assets could be accomplished through different sources, including malicious IPs, malicious or vulnerable firmware/software, unreliable and insecure interconnection and communication protocol, and side-channel vulnerabilities through power/performance profiles. Any unauthorized access to such highly sensitive assets may result in either a breach of company secrets for original equipment manufactures (OEM) or identity theft for the end-user. Unlike the enormous advances in functional testing and verification of the SoC architecture, security verification is still on the rise, and little endeavor has been carried out by academia and industry. Unfortunately, there exists a huge gap between the modernization of the SoC architectures and their security verification approaches. With the lack of automated SoC security verification in modern electronic design automation (EDA) tools, we provide a comprehensive overview of the requirements that must be realized as the fundamentals of the SoC security verification process in this paper. By reviewing these requirements, including the creation of a unified language for SoC security verification, the definition of security policies, formulation of the security verification, etc., we put forward a realization of the utilization of self-refinement techniques, such as fuzz, penetration, and AI testing, for security verification purposes. We evaluate all the challenges and resolution possibilities, and we provide the potential approaches for the realization of SoC security verification via these self-refinement techniques
Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs
Intellectual property (IP) cores are essential to creating modern system-on-chips (SoCs). Protecting the IPs deployed in modern SoCs has become more difficult as the IP houses have been established across the globe over the past three decades. The threat posed by IP piracy and overuse has been a topic of research for the past decade or so and has led to creation of a field called watermarking. IP watermarking aims of detecting unauthorized IP usage by embedding excess, nonfunctional circuitry into the SoC. Unfortunately, prior work has been built upon assumptions that cannot be met within the modern SoC design and verification processes. In this paper, we first provide an extensive overview of the current state-of-the-art IP watermarking. Then, we challenge these dated assumptions and propose a new path for future effective IP watermarking approaches suitable for today\u27s complex SoCs in which IPs are deeply embedded
A Survey on Security Threats and Countermeasures in IEEE Test Standards
International audienceEditor's note: Test infrastructure has been shown to be a portal for hackers. This article reviews the threats and countermeasures for IEEE test infrastructure standards
ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance
The semiconductor industry is entering a new age in which device scaling and cost reduction will no longer follow the decades-long pattern. Packing more transistors on a monolithic IC at each node becomes more difficult and expensive. Companies in the semiconductor industry are increasingly seeking technological solutions to close the gap and enhance cost-performance while providing more functionality through integration. Putting all of the operations on a single chip (known as a system on a chip, or SoC) presents several issues, including increased prices and greater design complexity. Heterogeneous integration (HI), which uses advanced packaging technology to merge components that might be designed and manufactured independently using the best process technology, is an attractive alternative. However, although the industry is motivated to move towards HI, many design and security challenges must be addressed. This paper presents a three-tier security approach for secure heterogeneous integration by investigating supply chain security risks, threats, and vulnerabilities at the chiplet, interposer, and system-in-package levels. Furthermore, various possible trust validation methods and attack mitigation were proposed for every level of heterogeneous integration. Finally, we shared our vision as a roadmap toward developing security solutions for a secure heterogeneous integration
Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation
The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation
Design for prognostics and security in field programmable gate arrays (FPGAs).
There is an evolutionary progression of Field Programmable Gate Arrays (FPGAs)
toward more complex and high power density architectures such as Systems-on-
Chip (SoC) and Adaptive Compute Acceleration Platforms (ACAP). Primarily, this is
attributable to the continual transistor miniaturisation and more innovative and
efficient IC manufacturing processes. Concurrently, degradation mechanism of Bias
Temperature Instability (BTI) has become more pronounced with respect to its
ageing impact. It could weaken the reliability of VLSI devices, FPGAs in particular
due to their run-time reconfigurability. At the same time, vulnerability of FPGAs to
device-level attacks in the increasing cyber and hardware threat environment is also
quadrupling as the susceptible reliability realm opens door for the rogue elements to
intervene. Insertion of highly stealthy and malicious circuitry, called hardware
Trojans, in FPGAs is one of such malicious interventions. On the one hand where
such attacks/interventions adversely affect the security ambit of these devices, they
also undermine their reliability substantially. Hitherto, the security and reliability are
treated as two separate entities impacting the FPGA health. This has resulted in
fragmented solutions that do not reflect the true state of the FPGA operational and
functional readiness, thereby making them even more prone to hardware attacks.
The recent episodes of Spectre and Meltdown vulnerabilities are some of the key
examples. This research addresses these concerns by adopting an integrated
approach and investigating the FPGA security and reliability as two inter-dependent
entities with an additional dimension of health estimation/ prognostics. The design
and implementation of a small footprint frequency and threshold voltage-shift
detection sensor, a novel hardware Trojan, and an online transistor dynamic scaling
circuitry present a viable FPGA security scheme that helps build a strong
microarchitectural level defence against unscrupulous hardware attacks. Augmented
with an efficient Kernel-based learning technique for FPGA health
estimation/prognostics, the optimal integrated solution proves to be more
dependable and trustworthy than the prevalent disjointed approach.Samie, Mohammad (Associate)PhD in Transport System