Buffer Management and Flow Control in the Credit Net ATM Host Interface

Among the many benefits of ATM networking are the potential for connections with negotiated quality-of-service (QoS) guarantees and application-specific data management at network endpoints. In this paper we describe the architecture of a PCI bus host adapter for OC-3 and OC-12 ATM, focusing on challenges in the areas of buffer management and flow control, since these are vital to realizing the bandwidth and QoS potential of ATM endpoint hosts. 1 Introduction This paper describes the architecture and implementation of the Credit Net ATM host adapter, which provides ATM connectivity at OC-3 and OC-12 rates to hosts with PCI I/O buses. The heart of the Credit Net adapter is an ASIC designed by the Intel Architecture Laboratories, based on an architecture designed jointly with the Credit Net group at Carnegie Mellon University. It provides support for SAR transmit and receive processing, AAL5 and software-defined AAL, transmit cell scheduling, host buffer management, and rate-based and ..