Power efficient H.264 video decoding in embedded multiprocessor

This thesis presents a novel methodology that enables power efficient video decoding in an embedded system based on MPSoC (Multiprocessor System on Chip). This methodology is a physical combination of parallel processing which reduces power consumption of processors by exploiting thread-level parallelism and Dynamic Voltage Frequency Scaling (DVFS) that allows a processor to dynamically change its speed and voltage at run time. The video decoding process must be well optimized to improve performance continuously due to the many complex computation units. Since these intense computation functions have their own specific patterns, they were mainly performed by specialized hardware device. This kind of device, one that combines a main processor and an Intellectual Property (IP), still dominates the multimedia market place because of its adjustable performance, power, and convenience of manufacturing, even though the powerful multi-core embedded processor was released the market a few years ago. Approach of this thesis exploits inherent advantages of the multiprocessor without additional hardware implementation, and presents a thorough analysis of video decoding process in an embedded system. A target application is H.264/AVC, a well-adapted video coding standard for current multimedia environments which is used for many portable devices