Bringing Network-on-Chip links to 45nm

The literature lacks of a comprehensive overview of achievable NoC link performance when key parameters are swept in the link microarchitecture and in the NoC floorplan. This paper bridges this basic gap while at the same time capturing how link performance is affected by the migration from a 65nm to a 45nm technology node. Finally, it identifies the requirements on EDA tools to keep up with the technology scaling