Board-level Multiterminal Net Routing for FPGA-based Logic Emulation

We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System [3] and the Enterprise Emulation System [5] manufactured by Quickturn Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets [10,11]. In this paper, we show how multi-terminal nets can be handled by decomposition into two-terminal nets. We show that the multi-terminal net decomposition problem can be modelled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed tospanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there isafeasible decomposition and gives one whenever such a decomposition exists