Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications

The latest results of benchmarking research are presented for a variety of beyond-CMOS charge- and spin-based devices. In addition to improving the device-level models, several new device proposals and a few majorly modified devices are investigated. Deep pipelining circuits are employed to boost the throughput of low-power devices. Furthermore, the benchmarking methodology is extended to interconnect-centric analyses and non-Boolean logic applications. In contrast to Boolean circuits, non-Boolean circuits based on the cellular neural network demonstrate that spintronic devices can potentially outperform conventional CMOS devices.Comment: 9 pages, 10 figure

Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation

We propose a heterostructure device comprised of magnets and piezoelectrics that significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low voltage operation, non-reciprocity, non-volatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21x shorter delay and 27x lower energy dissipation per bit for a 32-bit arithmetic-logic unit (ALU)

Voltage-Controlled Topological-Spin Switch for Ultra-Low-Energy Computing--Performance Modeling and Benchmarking

A voltage-controlled topological-spin switch (vTOPSS) that uses a hybrid topological insulator-magnetic insulator multiferroic is presented that can implement Boolean logic operations with sub-10 aJ energy-per-bit and energy-delay product on the order of $10^{-27}$ Js. The device uses a topological insulator (TI), which has the highest efficiency of conversion of electric field to spin torque yet observed at room temperature, and a low-moment magnetic insulator (MI) that can respond rapidly to a given spin torque. We present the theory of operation of vTOPSS, develop analytic models of its performance metrics, elucidate performance scaling with dimensions and voltage, and benchmark vTOPSS against existing spin-based and CMOS devices. Compared to existing spin-based devices, such as all-spin logic and charge-spin logic, vTOPSS offers 100$\times$ lower energy dissipation and (40-100)$\times$ lower energy-delay product. With experimental advances and improved material properties, we show that the energy-delay product of vTOPSS can be lowered to $10^{-29}$ Js, competitive against existing CMOS technology. Finally, we establish that interconnect issues that dominate the performance in CMOS logic are relatively less significant for vTOPSS, implying that highly resistive materials can indeed be used to interconnect vTOPSS devices.Comment: 12 pages, 10 figure

Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking

Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.Comment: 91 pages, 67 figures, 11 tables. Related to the conference presentation D. Nikonov and I. Young, Uniform Methodology for Benchmarking Beyond-CMOS Logic Devices, Proceedings of IEDM, 25.4 (2012

Perspectives of Using Oscillators for Computing and Signal Processing

It is an intriguing concept to use oscillators as fundamental building blocks of electronic computers. The idea is not new, but is currently subject to intense research as a part of the quest for 'beyond Moore' electronic devices. In this paper we give an engineering-minded survey of oscillator-based computing architectures, with the goal of understanding their promise and limitations for next-generation computing. We will mostly discuss non-Boolean, neurally-inspired computing concepts and put the emphasis on hardware and on circuits where the oscillators are realized from emerging, nanoscale building blocks. Despite all the promise that oscillatory computing holds, existing literature gives very few clear-cut arguments about the possible benefits of using oscillators in place of other analog nonlinear circuit elements. In this survey we will argue for finding the rationale of using oscillatory building blocks and call for benchmarking studies that compare oscillatory computing circuits to level-based (analog) implementations

Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition

We present a new circuit for non-Boolean recognition of binary images. Employing all-spin logic (ASL) devices, we design logic comparators and non-Boolean decision blocks for compact and efficient computation. By manipulation of fan-in number in different stages of the circuit, the structure can be extended for larger training sets or larger images. Operating based on the mainly similarity idea, the system is capable of constructing a mean image and compare it with a separate input image within a short decision time. Taking advantage of the non-volatility of ASL devices, the proposed circuit is capable of hybrid memory/logic operation. Compared with existing CMOS pattern recognition circuits, this work achieves a smaller footprint, lower power consumption, faster decision time and a lower operational voltage. To the best of our knowledge, this is the first fully spin-based complete pattern recognition circuit demonstrated using spintronic devices.Comment: This article is accepted to appear in IEEE Transactions on Nanotechnolog

Proposal For Neuromorphic Hardware Using Spin Devices

We present a design-scheme for ultra-low power neuromorphic hardware using emerging spin-devices. We propose device models for 'neuron', based on lateral spin valves and domain wall magnets that can operate at ultra-low terminal voltage of ~20 mV, resulting in small computation energy. Magnetic tunnel junctions are employed for interfacing the spin-neurons with charge-based devices like CMOS, for large-scale networks. Device-circuit co-simulation-framework is used for simulating such hybrid designs, in order to evaluate system-level performance. We present the design of different classes of neuromorphic architectures using the proposed scheme that can be suitable for different applications like, analog-data-sensing, data-conversion, cognitive-computing, associative memory, programmable-logic and analog and digital signal processing. We show that the spin-based neuromorphic designs can achieve 15X-300X lower computation energy for these applications; as compared to state of art CMOS designs

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks

In this paper, a spintronic neuromorphic reconfigurable Array (SNRA) is developed to fuse together power-efficient probabilistic and in-field programmable deterministic computing during both training and evaluation phases of restricted Boltzmann machines (RBMs). First, probabilistic spin logic devices are used to develop an RBM realization which is adapted to construct deep belief networks (DBNs) having one to three hidden layers of size 10 to 800 neurons each. Second, we design a hardware implementation for the contrastive divergence (CD) algorithm using a four-state finite state machine capable of unsupervised training in N+3 clocks where N denotes the number of neurons in each RBM. The functionality of our proposed CD hardware implementation is validated using ModelSim simulations. We synthesize the developed Verilog HDL implementation of our proposed test/train control circuitry for various DBN topologies where the maximal RBM dimensions yield resource utilization ranging from 51 to 2,421 lookup tables (LUTs). Next, we leverage spin Hall effect (SHE)-magnetic tunnel junction (MTJ) based non-volatile LUTs circuits as an alternative for static random access memory (SRAM)-based LUTs storing the deterministic logic configuration to form a reconfigurable fabric. Finally, we compare the performance of our proposed SNRA with SRAM-based configurable fabrics focusing on the area and power consumption induced by the LUTs used to implement both CD and evaluation modes. The results obtained indicate more than 80% reduction in combined dynamic and static power dissipation, while achieving at least 50% reduction in device count.Comment: 8 page

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Protecting intellectual property (IP) has become a serious challenge for chip designers. Most countermeasures are tailored for CMOS integration and tend to incur excessive overheads, resulting from additional circuitry or device-level modifications. On the other hand, power density is a critical concern for sub-50 nm nodes, necessitating alternate design concepts. Although initially tailored for error-tolerant applications, imprecise computing has gained traction as a general-purpose design technique. Emerging devices are currently being explored to implement ultra-low-power circuits for inexact computing applications. In this paper, we quantify the security threats of imprecise computing using emerging devices. More specifically, we leverage the innate polymorphism and tunable stochastic behavior of spin-orbit torque (SOT) devices, particularly, the giant spin-Hall effect (GSHE) switch. We enable IP protection (by means of logic locking and camouflaging) simultaneously for deterministic and probabilistic computing, directly at the GSHE device level. We conduct a comprehensive security analysis using state-of-the-art Boolean satisfiability (SAT) attacks; this study demonstrates the superior resilience of our GSHE primitive when tailored for deterministic computing. We also demonstrate how probabilistic computing can thwart most, if not all, existing SAT attacks. Based on this finding, we propose an attack scheme called probabilistic SAT (PSAT) which can bypass the defense offered by logic locking and camouflaging for imprecise computing schemes. Further, we illustrate how careful application of our GSHE primitive can remain secure even on the application of the PSAT attack. Finally, we also discuss side-channel attacks and invasive monitoring, which are arguably even more concerning threats than SAT attacks.Comment: To be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and System

Magnonic Holographic Memory: from Proposal to Device

In this work, we present recent developments in magnonic holographic memory devices exploiting spin waves for information transfer. The devices comprise a magnetic matrix and spin wave generating/detecting elements placed on the edges of the waveguides. The matrix consists of a grid of magnetic waveguides connected via cross junctions. Magnetic memory elements are incorporated within the junction while the read-in and read-out is accomplished by the spin waves propagating through the waveguides. We present experimental data on spin wave propagation through NiFe and YIG magnetic crosses. The obtained experimental data show prominent spin wave signal modulation (up to 20 dB for NiFe and 35 dB for YIG) by the external magnetic field, where both the strength and the direction of the magnetic field define the transport between the cross arms. We also present experimental data on the 2-bit magnonic holographic memory built on the double cross YIG structure with micro-magnets placed on the top of each cross. It appears possible to recognize the state of each magnet via the interference pattern produced by the spin waves with all experiments done at room temperature. Magnonic holographic devices aim to combine the advantages of magnetic data storage with wave-based information transfer. We present estimates on the spin wave holographic devices performance, including power consumption and functional throughput. According to the estimates, magnonic holographic devices may provide data processing rates higher than 10^18 bits/cm2/s while consuming 0.15uW. Technological challenges and fundamental physical limits of this approach are also discussed