CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip

Quantum computing is experiencing the transition from a scientific to an engineering field with the promise to revolutionize an extensive range of applications demanding high-performance computing. Many implementation approaches have been pursued for quantum computing systems, where currently the main streams can be identified based on superconducting, photonic, trapped-ion, and semiconductor qubits. Semiconductor-based quantum computing, specifically using CMOS technologies, is promising as it provides potential for the integration of qubits with their control and readout circuits on a single chip. This paves the way for the realization of a large-scale quantum computing system for solving practical problems. In this paper, we present an overview and future perspective of CMOS quantum computing, exploring developed semiconductor qubit structures, quantum gates, as well as control and readout circuits, with a focus on the promises and challenges of CMOS implementation

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs

Quantum Parametric Amplification and NonClassical Correlations due to 45 nm nMOS Circuitry Effect

This study unveils a groundbreaking exploration of using semiconductor technology in quantum circuitry. Leveraging the unique operability of 45 nm CMOS technology at deep cryogenic temperatures (~ 300 mK), a novel quantum electronic circuit is meticulously designed. Through the intricate coupling of two matching circuits via a 45 nm nMOS transistor, operating as an open quantum system, the circuit quantum Hamiltonian and the related Heisenberg-Langevin equation are derived, setting the stage for a comprehensive quantum analysis. Central to this investigation are three pivotal coefficients derived, which are the coupling between the coupled oscillator charge and flux operators through the internal circuit of the transistor. These coefficients emerge as critical determinants, shaping both the circuit potential as a parametric amplifier and its impact on quantum properties. The study unfolds a delicate interplay between these coefficients, showcasing their profound influence on quantum discord and the gain of the parametric amplifier. Consequently, the assimilation of 45 nm CMOS technology with quantum circuitry makes it possible to potentially bridge the technological gap in quantum computing applications, where the parametric amplifier is a necessary and critical device. The designed novel quantum device serves not only as a quantum parametric amplifier to amplify quantum signals but also enhances the inherent quantum properties of the signals such as non-classicality. Therefore, one can create an effective parametric amplifier that simultaneously improves the quantum characteristics of the signals. The more interesting result is that if such a theory becomes applicable, the circuit implemented in the deep-cryogenic temperature can be easily compatible with the next step of circuitry while keeping the same electronic features compatibility with the quantum processor.Comment: 11 pages, 5 figure

Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.Comment: Comments welcom

Circuit-Based Compact Model of Electron Spin Qubit

Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed

Low-Power HEMT LNAs for Quantum Computing

The rapid development of quantum computing technology predicts much more qubits to handle in the detection, readout, and amplification of qubits than in today\u27s system. Due to the limited cooling capability of the dilution refrigerator, the current low-noise amplifiers (LNAs) are in need of ten to hundred times reduced dc power consumption yet with lowest noise temperature at qubit readout frequencies, typcially 4-12 GHz. Cryogenic indium phosphide (InP) high electron mobility transistor (HEMT) LNAs, are the standard qubit amplifier at 4 K in today\u27s superconducting quantum system. However, the power consumption of current InP HEMT LNAs is still too high for future quantum system up-scaling.A small-signal noise model of a 100-nm gate-length InP HEMTs has been characterized and extracted at 4 K ambient under low-power bias down to 1 μW. The extracted low-power small-signal noise models revealed fast degradation points of drain voltage bias for RF and noise performance.The design goals of the cryogenic LNA were tailored for a superconducting qubit readout application based on the extracted low-power small-signal noise model of the InP HEMT for optimum noise and power consumption trade-off. A cryogenic InP HEMT hybrid LNA operating in the 4-6 GHz frequency range at 200 μW with an average noise temperature of 2.0 K has been designed, fabricated, and successfully demonstrated, validating the extracted model and design methodology.An epitaxially-optimized InP HEMT was modeled with the low-power methodology. The comparison of the small-signal noise model parameters to the standard InP HEMT showed improved transconductance, matching, and noise at the same bias power. The demonstrated three-stage cryogenic 4-6 GHz LNA equipped with an optimized HEMT as the first stage achieved 2.0 K average noise temperature at 100 μW dc power dissipation, representing a new state-of-the-art. This licentiate thesis has presented experimental evidence that there is large potential in reducing dc power in the cryogenic InP HEMT LNA for qubit readout which can be important for the planned up-scaling in future quantum computing

Scalable and high-sensitivity readout of silicon quantum devices

Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems

Is there a Moore's law for quantum computing?

There is a common wisdom according to which many technologies can progress according to some exponential law like the empirical Moore's law that was validated for over half a century with the growth of transistors number in chipsets. As a still in the making technology with a lot of potential promises, quantum computing is supposed to follow the pack and grow inexorably to maturity. The Holy Grail in that domain is a large quantum computer with thousands of errors corrected logical qubits made themselves of thousands, if not more, of physical qubits. These would enable molecular simulations as well as factoring 2048 RSA bit keys among other use cases taken from the intractable classical computing problems book. How far are we from this? Less than 15 years according to many predictions. We will see in this paper that Moore's empirical law cannot easily be translated to an equivalent in quantum computing. Qubits have various figures of merit that won't progress magically thanks to some new manufacturing technique capacity. However, some equivalents of Moore's law may be at play inside and outside the quantum realm like with quantum computers enabling technologies, cryogeny and control electronics. Algorithms, software tools and engineering also play a key role as enablers of quantum computing progress. While much of quantum computing future outcomes depends on qubit fidelities, it is progressing rather slowly, particularly at scale. We will finally see that other figures of merit will come into play and potentially change the landscape like the quality of computed results and the energetics of quantum computing. Although scientific and technological in nature, this inventory has broad business implications, on investment, education and cybersecurity related decision-making processes.Comment: 32 pages, 24 figure