Adaptive market hypothesis

Purpose: To investigate the implications of the Addaptive Market Hypothesis (AMH) on Turkish stock exchange market (Borsa Istanbul) indices as an emerging economy. BIST-100, BIST-30 and BIST-All indices are subjected to the analyses for the period between January 2002 and April 2017. Design/Methodology/Approach: Two-year rolling windows and daily test values were calculated by using linear methods (Variance Ratio Test) and nonlinear methods (BDS test) to investigate the market efficiency. Findings: According to the Variance Ratio Test results, index returns are unpredictable, that is, the market is efficient, while the results of nonlinear analysis show the existence of adaptive market hypothesis. In particular, all three indices display efficiency in the 2013-2016 period implying that returns were not predictable in this period. The results of the non-linear analysis show that the market is efficient from time to time and sometimes deviates from efficiency, indicating the validity of the adaptive market hypothesis in Borsa Istanbul. Practical Implications: The changes in the market efficiency from time to time should be considered while taking important investment decisions. Moreover, according to AMH, since trends, panics, bubbles and crashes exist in the market, arbitrage opportunities arise time to time, and market timing is an important issue to catch the profit opportunities. Therefore, as a further study, matching the important events with the efficiency of the market could provide more insights about timing the market. Originality/Value: To the best of authors’ knowledge, this is the first comprehensive study that examines the index based AMH in Borsa Istanbul. This study is believed to contribute to the literature by giving insights about the evolution of market efficiency in Turkey.peer-reviewe

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

A non-projective greedy dependency parser with bidirectional LSTMs

The LyS-FASTPARSE team presents BIST-COVINGTON, a neural implementation of the Covington (2001) algorithm for non-projective dependency parsing. The bidirectional LSTM approach by Kipperwasser and Goldberg (2016) is used to train a greedy parser with a dynamic oracle to mitigate error propagation. The model participated in the CoNLL 2017 UD Shared Task. In spite of not using any ensemble methods and using the baseline segmentation and PoS tagging, the parser obtained good results on both macro-average LAS and UAS in the big treebanks category (55 languages), ranking 7th out of 33 teams. In the all treebanks category (LAS and UAS) we ranked 16th and 12th. The gap between the all and big categories is mainly due to the poor performance on four parallel PUD treebanks, suggesting that some `suffixed' treebanks (e.g. Spanish-AnCora) perform poorly on cross-treebank settings, which does not occur with the corresponding `unsuffixed' treebank (e.g. Spanish). By changing that, we obtain the 11th best LAS among all runs (official and unofficial). The code is made available at https://github.com/CoNLL-UD-2017/LyS-FASTPARSEComment: 12 pages, 2 figures, 5 table

Design of High-Speed Multiplier with Optimised Builtinself-Test

Current trend in Integrated Circuits (IC) implementation such as System-on-Chip has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Since the development of System-on-Chip, which is based on integrating subsystems supplied by various Intellectual Properties (IP) Block vendors, the required design time is shorter when compared to that of full-custom IC implementation. However, testing each internal subsystems using the common scan-path method where test data are generated and analyzed externally is considered too time consuming when the number of subsystems is high. Therefore, by including Built-In-Self-Test (BIST) facility into each subsystem is considered a good solution. Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. Since t he number of subsystems in an IC chip is going to be increased from time to time, improvement on the BIST approach is required to provide shorter testing time while keeping the good features of LFSR. For this reason, development of test pattern for BIST based on combination of LFSR and deterministic approach could provide one of the solutions to reduce the testing time. In this research, the possibility of combining LFSR features and deterministic test pattern was carried out. A parallel high-speed multiplier considered as one of the demanding subsystems was chosen to verify the proposed BIST performance. Results show that the testing time (with 100% fault coverage) was reduced significantly when compared to the testing time taken for the BIST that was totally based on random test data generation. One of the reasons for this achievement is only one basic cell of the multiplier is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both multiplier inputs simultaneously. This is the significant finding of the research. Further works based on the finding are also identified

Bridging the Testing Speed Gap: Design for Delay Testability

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addresse

Testing Embedded Memories in Telecommunication Systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presente

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

A Self-Repairing Execution Unit for Microprogrammed Processors

Describes a processor which dynamically reconfigures its internal microcode to execute each instruction using only fault-free blocks from the execution unit. Working without redundant or spare computational blocks, this self-repair approach permits a graceful performance degradatio