High-Level Design for Ultra-Fast Software Defined Radio Prototyping on Multi-Processors Heterogeneous Platforms

International audienceThe design of Software Defined Radio (SDR) equipments (terminals, base stations, etc.) is still very challenging. We propose here a design methodology for ultra-fast prototyping on heterogeneous platforms made of GPPs (General Purpose Processors), DSPs (Digital Signal Processors) and FPGAs (Field Programmable Gate Array). Lying on a component-based approach, the methodology mainly aims at automating as much as possible the design from an algorithmic validation to a multi-processing heterogeneous implementation. The proposed methodology is based on the SynDEx CAD design approach, which was originally dedicated to multi-GPPs networks. We show how this was changed so that it is made appropriate with an embedded context of DSP. The implication of FPGAs is then addressed and integrated in the design approach with very little restrictions. Apart from a manual HW/SW partitioning, all other operations may be kept automatic in a heterogeneous processing context. The targeted granularity of the components, which are to be assembled in the design flow, is roughly the same size as that of a FFT, a filter or a Viterbi decoder for instance. The re-use of third party or pre-developed IPs is a basis for this design approach. Thanks to the proposed design methodology it is possible to port "ultra" fast a radio application over several platforms. In addition, the proposed design methodology is not restricted to SDR equipment design, and can be useful for any real-time embedded heterogeneous design in a prototyping context

hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms

Developing heterogeneous multicore platforms requires choosing the best hardware configuration for mapping the application, and modifying that application so that different parts execute on the most appropriate hardware component. The hArtes toolchain provides the option of automatic or semi-automatic support for this mapping. During test and validation on several computation-intensive applications, hArtes achieved substantial speedups and drastically reduced development times

RTRLIB : a high-level modeling tool for dynamically partially reconfigurable systems

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2020.Reconfiguração dinâmica parcial é considerada uma interessante técnica a ser aplicada para o aumento da flexibilidade de sistemas implementados em FPGA, em função da implementação dinâmica de módulos de hardware enquanto o restante do circuito permanece em operação. Trata- se de uma técnica utilizada em sistemas com requisitos muito restritos, como adaptabilidade, robustez, consumo de potência, custo e tolerância à falhas. Entretanto, a complexidade de desen- volvimento de sistemas com reconfiguração dinâmica parcial é consideravelmente alta quando comparada à de sistemas com lógica totalmente estática. Nesse sentido, novas metodologias e ferramentas de desenvolvimento são necessárias para reduzir a complexidade de implementação desse tipo de sistema. Nesse contexto, esse trabalho apresenta o RTRLib, uma ferramenta de modelagem em alto nível para o desenvolvimento de sistemas com reconfiguração dinâmica parcial em dispositivos Xilinx Zynq a partir da especificação e parametrização de alguns blocos. Sob condições específi- cas, o RTRLib automaticamante produz os scripts de hardware e software para implementação da solução utilizando o Vivado Design Suite e o SDK. Tais scripts são compostos pelos comandos necessários para a implementação do sistema desde a criação do projeto de hardware até a criação do arquivo de boot. Uma vez que o RTRLib é composto por IP-Cores previamente caracterizados, a ferramenta também pode ser utilizada para a análise, em fase de modelagem, do sistema a ser implementado, por meio da estimação de características importantes do sistema, como o consumo de recursos e latência. O presente trabalho também inclui novas funcionalidades implementadas no RTRLib no con- texto do design de hardware e de software, como: generalização do script de hardware, mapea- mento de IO, floorplanning por meio de uma GUI, criação de um gerador de script de software, gerador de template de aplicação standalone que faz uso do partial reconfiguration controller (PRC) e implementação de uma biblioteca para aplicações FreeRTOS. Por fim, quatro estudos de casos foram implementados para demonstrar as funcionalidades da ferramenta: um sistema de classificação de terrenos baseado em redes neurais, um sistema com regressores lineares utilizado para controle de uma prótese miocinética de mão e, por último, uma aplicação hipotética de um sistema com requisitos de tempo real.Partial dynamic reconfiguration is considered an interesting technique to increase flexibility in FPGA designs due to the dynamic replacement of hardware modules while the remainder of the circuit remains in operation. It is used in systems with hard requirements such as adaptability, robustness, power consumption, cost, and fault-tolerance. However, the complexity to develop dynamically partially reconfigurable systems in considerably higher comparing with static de- signs. Therefore, new design methodologies and tools have been required to reduce the design complexity of such systems. In this context, this work presents the RTRLib, a high-level modeling tool for the development of dynamically reconfigurable systems on Xilinx Zynq devices by a simple system specification and parametrization of some blocks. Under specific conditions, RTRLib automatically generates the hardware and software scripts to implement the solution using Vivado and SDK. These scripts are composed by the sequential design steps from hardware project creation to the boot image elaboration. Since RTRLib is composed of pre-characterized IP-Cores, the tool also can be used to analyze the system behavior during the design process by the early estimation of essential characteristics of the system such as resource consumption and latency. The present work also includes the new functionalities implemented on RTRLib in the context of the hardware and the software design, such as: hardware script generalization, IO mapping, floorplanning by a GUI, software script creation, generator of a standalone template application that uses PRC, and implementation of a FreeRTOS library application. Finally, four case studies were implemented to demonstrate the tool capability: a system for terrain classification based on neuron networks, a linear regressor system used to control a myokinetic-based prosthetic hand, and a hypothetical real-time application

Methodology for complex dataflow application development

This thesis addresses problems inherent to the development of complex applications for reconfig- urable systems. Many projects fail to complete or take much longer than originally estimated by relying on traditional iterative software development processes typically used with conventional computers. Even though designer productivity can be increased by abstract programming and execution models, e.g., dataflow, development methodologies considering the specific properties of reconfigurable systems do not exist. The first contribution of this thesis is a design methodology to facilitate systematic develop- ment of complex applications using reconfigurable hardware in the context of High-Performance Computing (HPC). The proposed methodology is built upon a careful analysis of the original application, a software model of the intended hardware system, an analytical prediction of performance and on-chip area usage, and an iterative architectural refinement to resolve identi- fied bottlenecks before writing a single line of code targeting the reconfigurable hardware. It is successfully validated using two real applications and both achieve state-of-the-art performance. The second contribution extends this methodology to provide portability between devices in two steps. First, additional tool support for contemporary multi-die Field-Programmable Gate Arrays (FPGAs) is developed. An algorithm to automatically map logical memories to hetero- geneous physical memories with special attention to die boundaries is proposed. As a result, only the proposed algorithm managed to successfully place and route all designs used in the evaluation while the second-best algorithm failed on one third of all large applications. Second, best practices for performance portability between different FPGA devices are collected and evaluated on a financial use case, showing efficient resource usage on five different platforms. The third contribution applies the extended methodology to a real, highly demanding emerging application from the radiotherapy domain. A Monte-Carlo based simulation of dose accumu- lation in human tissue is accelerated using the proposed methodology to meet the real time requirements of adaptive radiotherapy.Open Acces

A Survey and Evaluation of FPGA High-Level Synthesis Tools

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources

Design and testing methodologies for signal processing systems using DICE

The design and integration of embedded systems in heterogeneous programming environments is still largely done in an ad hoc fashion making the overall development process more complicated, tedious and error-prone. In this work, we propose enhancements to existing design flows that utilize model-based design to verify cross-platform correctness of individual actors. The DSPCAD Integrative Command Line Environment (DICE) is a realization of managing these enhancements. We demonstrate this design flow with two case studies. By using DICE's novel test framework on modules of a triggering system in the Large Hadron Collider, we demonstrate how the cross-platform model-based approach, automatic testbench creation and integration of testing in the design process alleviate the rigors of developing such a complex digital system. The second case study is an exploration study into the required precision for eigenvalue decomposition using the Jacobi algorithm. This case study is a demonstration of the use of dataflow modeling in early stage application exploration and the use of DICE in the overall design flow