Automatic power modeling of infrastructure IP for system-on-chip power analysis

Modern System-on-Chips (SoCs) are often designed under stringent time-to-market constraints. Hence, they are realized by re-using a number of pre-designed components (or IP blocks) that implement standard, yet critical functions. An important category of IP blocks are the so-called Infrastructure IP (IIP) blocks, which include interfaces to off-chip memory, I/O devices, and peripherals, as well as hardware to provide DMA transfers, interrupts, timing, etc. IIP components are often responsible for a substantial portion of a SoC?s power consumption, making it important to model and consider their effect in power-aware SoC design. However, system-level power analysis and optimization has, for the most part, focused on the processor, memory hierarchy, interconnect, and application-specific hardware. Relatively little work has addressed modeling the power consumed by these Infrastructure IP (IIP) components, or their impact on system-level tradeoffs. This paper describes a systematic methodology to automatically generate power models for IIP components for use in system-level power analysis and optimization tools. Our methodology starts with (i) a high-level functional model of an IIP component designed for fast simulation, and (ii) a corresponding implementation model (RTL or gate-level description), from which accurate power estimates can be obtained. It automatically generates an enhanced version of the high-level functional model, which includes an accurate, yet efficient power model. This paper describes the key steps of the methodology, and presents techniques based on statistical analysis and symbolic regression to automate the most labor-intensive steps. The proposed methodology has been applied to several commercial IIP designs, including ones from the Synopsys Design- Ware library. The resulting power models produce estimates that are within 7% of gate-level power analysis, while being several hundred times faster, making them highly suitable for system-level power analysis. Moreover, the use of an automatic methodology drastically reduces the effort spent in power model development, from over a week to under an hour in some cases. The automatically generated models have been integrated into an in-house system-level power estimation framework. We demonstrate their utility in exploring system-level design tradeoffs using an example SoC design

Une méthode d'estimation de la consommation de puissance pour un système sur puce

RÉSUMÉ Estimer la consommation de puissance le plus tôt possible durant le cycle de développement est important pour pouvoir rencontrer le temps de mise en marché. Pour cela, plusieurs recherches en consommation de puissance se tournent vers l'estimation à haut niveau, comme la Modélisation au Niveau Transactionnel (TLM), pour accélérer l’obtention des estimations de puissance. Ce travail présente une méthodologie à haut-niveau orienté sur les Coeur sous licence (IP) qui effectue une estimation de puissance. La méthode propose une distinction entre l'activité de l'IP concerné et de son implémentation. Ceci permet de facilement créer un modèle qui peut être réutilisé avec différentes fréquences et implémentations. En utilisant l'information obtenue par des mesures d'une description au Niveau Registre (RTL), un modèle peut-être créé pour des simulations haut-niveau permettant d'abstraire l'implémentation. La méthodologie est présentée sur un processeur, une mémoire, un bus, une minuterie et un Contrôleur d'Interruption de Processeur (PIC) de Xilinx. En comparaison à des estimations effectuées au niveau RTL, le modèle permet d'estimer la consommation de puissance avec une précision de 25 ±10% par rapport à une estimation effectuée avec Xpower; et ce avec un facteur accélération de trois ou quatre ordres de grandeur.---------- ABSTRACT Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like the Transaction-Level Modeling (TLM), to estimate power earlier. This work presents a high-level Intellectual Property core (IP) oriented power estimation methodology. The methodology separates the activity of the IP from the implementation. This allows the ability to easily create a model that can be used with different frequencies, layout and implementation technology. By using data gathered from the Register-Transfer Level (RTL) a model can be created for high-level simulation that can take into account the technology and characteristics of the Field-Programmable Gate Array (FPGA) device. The methodology is presented in this work for a processor, its local memory IP, counter, Processor Interrupt Controller (PIC) and bus from Xilinx. Compared to estimations made at the RTL level, the resulting model gives accurate results of 25% ±10% compared to a Xpower estimate with three to four order speedups and through different implementations

Automatic power modeling of infrastructure IP for system-on-chip power analysis

Modern System-on-Chips (SoCs) are often designed under stringent time-to-market constraints. Hence, they are realized by re-using a number of pre-designed components (or IP blocks) that implement standard, yet critical functions. An important category of IP blocks are the so-called Infrastructure IP (IIP) blocks, which include interfaces to off-chip memory, I/O devices, and peripherals, as well as hardware to provide DMA transfers, interrupts, timing, etc. IIP components are often responsible for a substantial portion of a SoC?s power consumption, making it important to model and consider their effect in power-aware SoC design. However, system-level power analysis and optimization has, for the most part, focused on the processor, memory hierarchy, interconnect, and application-specific hardware. Relatively little work has addressed modeling the power consumed by these Infrastructure IP (IIP) components, or their impact on system-level tradeoffs. This paper describes a systematic methodology to automatically generate power models for IIP components for use in system-level power analysis and optimization tools. Our methodology starts with (i) a high-level functional model of an IIP component designed for fast simulation, and (ii) a corresponding implementation model (RTL or gate-level description), from which accurate power estimates can be obtained. It automatically generates an enhanced version of the high-level functional model, which includes an accurate, yet efficient power model. This paper describes the key steps of the methodology, and presents techniques based on statistical analysis and symbolic regression to automate the most labor-intensive steps. The proposed methodology has been applied to several commercial IIP designs, including ones from the Synopsys Design- Ware library. The resulting power models produce estimates that are within 7% of gate-level power analysis, while being several hundred times faster, making them highly suitable for system-level power analysis. Moreover, the use of an automatic methodology drastically reduces the effort spent in power model development, from over a week to under an hour in some cases. The automatically generated models have been integrated into an in-house system-level power estimation framework. We demonstrate their utility in exploring system-level design tradeoffs using an example SoC design