1 research outputs found
Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation
Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by
partitioning it into a number of coupled sub-FSMs where only the part that is involved
in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a
partitioning algorithm and sub-FSM synthesis to an implementation architecture. In
this paper, we first introduce an implementation architecture for partitioned FSMs that
uses gated-clock technique for disabling idle parts of the circuits and asynchronous
controllers for communication between the sub-FSMs. We then describe a new transformation
procedure for the sub-FSM. The FSM synthesis flow has been automated in a
prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level
VHDL code with identical cycle-to-cycle input/output behavior in accordance
with the specification. An average power reduction of 45% has been obtained for a set
standard FSM benchmarks