5 research outputs found
Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic
A new asynchronous early output section-carry based carry lookahead adder
(SCBCLA) with alias carry output logic is presented in this paper. To evaluate
the proposed SCBCLA with alias carry logic and to make a comparison with other
CLAs, a 32-bit addition operation is considered. Compared to the
weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with
alias logic reports a 13% reduction in area without any increases in latency
and power dissipation. On the other hand, in comparison with the early output
recursive CLA (RCLA), the proposed early output SCBCLA with alias logic reports
a 16% reduction in latency while occupying almost the same area and dissipating
almost the same average power. All the asynchronous CLAs are
quasi-delay-insensitive designs which incorporate the delay-insensitive
dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking.
The adders were realized and the simulations were performed based on a 32/28nm
CMOS process
Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results
A new asynchronous early output block carry lookahead adder (BCLA)
incorporating redundant carries is proposed. Compared to the best of existing
semi-custom asynchronous carry lookahead adders (CLAs) employing
delay-insensitive data encoding and following a 4-phase handshaking, the
proposed BCLA with redundant carries achieves 13% reduction in forward latency
and 14.8% reduction in cycle time compared to the best of the existing CLAs
featuring redundant carries with no area or power penalty. A hybrid variant
involving a ripple carry adder (RCA) in the least significant stages i.e.
BCLA-RCA is also considered that achieves a further 4% reduction in the forward
latency and a 2.4% reduction in the cycle time compared to the proposed BCLA
featuring redundant carries without area or power penalties
Critique of "Asynchronous Logic Implementation Based on Factorized DIMS"
This paper comments on "Asynchronous Logic Implementation Based on Factorized
DIMS" [Journal of Circuits, Systems, and Computers, vol. 26, no. 5, 1750087:
1-9, May 2017] with respect to two main problematic issues: i) the gate orphan
problem implicit in the factorized DIMS approach discussed in the referenced
article which affects its strong-indication, and ii) how the enumeration of
product terms to represent the synthesis cost is skewed in the referenced
article because the logic expression contains sum of products and also product
of sums. It is observed that the referenced article has not provided a general
logic synthesis algorithm excepting only an example illustration involving a
3-input AND logic function. The absence of a general logic synthesis algorithm
would make it difficult to reproduce the research described in the referenced
article. Moreover, the example illustration in the referenced article describes
an unsafe logic decomposition which is not suitable for the multi-level
synthesis of strong-indication asynchronous circuits. Further, a logic
synthesis method which safely decomposes the DIMS solution to synthesize
multi-level strong-indication asynchronous circuits is available in the
existing literature, which was neither cited nor taken up for comparison in the
referenced article, which is another drawback. Subsequently, it is concluded
that the referenced article has not advanced existing knowledge in the field
but on the contrary, has caused confusions. Hence, in the interest of readers,
this paper additionally highlights some important and relevant literature which
provide valuable information about robust asynchronous circuit synthesis
techniques which employ delay-insensitive codes for data representation and
processing and the 4-phase return-to-zero handshake protocol for data
communication.Comment: 15 page
Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders
In this technical note, we provide a comparison of the design metrics of
various quasi-delay-insensitive (QDI) asynchronous adders, where the adders
correspond to diverse architectures. QDI adders are robust, and the objective
of this technical note is to point to those QDI adders which are suitable for
low power/energy and less area. This information could be valuable for a
resource-constrained low power VLSI design scenario. Non-QDI adders are
excluded from the comparison since they are not robust although they may have
optimized design metrics. All the QDI adders were realized using a 32/28nm CMOS
process.Comment: arXiv admin note: substantial text overlap with arXiv:1903.0943
Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder
We present a new asynchronous quasi-delay-insensitive (QDI) block carry
lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive
dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase
return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster
and energy-efficient than the existing asynchronous adders which are QDI and
non-QDI (i.e., relative-timed). Compared to existing asynchronous adders
corresponding to various architectures such as ripple carry adder (RCA),
conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC,
and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more
energy-optimised. The cycle time (CT), which is the sum of forward and reverse
latencies, governs the speed; and the product of average power dissipation and
cycle time viz. the power-cycle time product (PCTP) defines the low
power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC
achieves the following average reductions in design metrics over its
counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6%
reductions in CT and PCTP respectively compared to an optimum QDI early output
RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an
optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP
respectively compared to an optimum uniform input-partitioned QDI early output
CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an
optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP
respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and
11.6% reductions in CT and PCTP respectively compared to an optimum QDI early
output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS
technology.Comment: PLOS ONE Preprint versio