141 research outputs found

    MOCAST 2021

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    The 10th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2021) will take place in Thessaloniki, Greece, from July 5th to July 7th, 2021. The MOCAST technical program includes all aspects of circuit and system technologies, from modeling to design, verification, implementation, and application. This Special Issue presents extended versions of top-ranking papers in the conference. The topics of MOCAST include:Analog/RF and mixed signal circuits;Digital circuits and systems design;Nonlinear circuits and systems;Device and circuit modeling;High-performance embedded systems;Systems and applications;Sensors and systems;Machine learning and AI applications;Communication; Network systems;Power management;Imagers, MEMS, medical, and displays;Radiation front ends (nuclear and space application);Education in circuits, systems, and communications

    The Fifteenth Marcel Grossmann Meeting

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    The three volumes of the proceedings of MG15 give a broad view of all aspects of gravitational physics and astrophysics, from mathematical issues to recent observations and experiments. The scientific program of the meeting included 40 morning plenary talks over 6 days, 5 evening popular talks and nearly 100 parallel sessions on 71 topics spread over 4 afternoons. These proceedings are a representative sample of the very many oral and poster presentations made at the meeting.Part A contains plenary and review articles and the contributions from some parallel sessions, while Parts B and C consist of those from the remaining parallel sessions. The contents range from the mathematical foundations of classical and quantum gravitational theories including recent developments in string theory, to precision tests of general relativity including progress towards the detection of gravitational waves, and from supernova cosmology to relativistic astrophysics, including topics such as gamma ray bursts, black hole physics both in our galaxy and in active galactic nuclei in other galaxies, and neutron star, pulsar and white dwarf astrophysics. Parallel sessions touch on dark matter, neutrinos, X-ray sources, astrophysical black holes, neutron stars, white dwarfs, binary systems, radiative transfer, accretion disks, quasars, gamma ray bursts, supernovas, alternative gravitational theories, perturbations of collapsed objects, analog models, black hole thermodynamics, numerical relativity, gravitational lensing, large scale structure, observational cosmology, early universe models and cosmic microwave background anisotropies, inhomogeneous cosmology, inflation, global structure, singularities, chaos, Einstein-Maxwell systems, wormholes, exact solutions of Einstein's equations, gravitational waves, gravitational wave detectors and data analysis, precision gravitational measurements, quantum gravity and loop quantum gravity, quantum cosmology, strings and branes, self-gravitating systems, gamma ray astronomy, cosmic rays and the history of general relativity

    Impact of using approximate FP multipliers in a neural network

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    En els Ășltims anys, computaciĂł aproximada ha estat un dels temes mĂ©s populars en camps com el reconeixement d'imatges, l'anĂ lisi d'imatges, el processament del llenguatge. Molts cientĂ­fics han estat estudiant com aprofitar l’Ășs d’unitats aritmĂštiques aproximades per millorar l'eficiĂšncia, reduir el consum d'energia i els retards en implementacions de xarxes neuronals. En aquesta tesi proposem tres multiplicadors aproximats per la multiplicaciĂł de les mantisses. El primer estĂ  dissenyat per reduir el nombre de cĂ lculs posant una part del resultat a un valor constant determinat. El segon Ă©s el multiplicador logarĂ­tmic de Mitchell i el tercer Ă©s el multiplicador logarĂ­tmic amb un carry per compensar l'error negatiu que provoca el multiplicador logarĂ­tmic. Per a avaluar aquests tres multiplicadors, utilitzarem la xarxa neuronal YOLOv3, basada en el framework de xarxa neuronal de codi obert que s'anomena Darknet. Aquest framework estĂ  dedicat a fer reconeixement d'objectes d'imatges.In the last few years, approximate computing has been one of the most popular topics in fields like image recognition, image analysis, language processing, self- driving, etc. Many scientists have been studying how to make use of approximate arithmetic units to improve the efficiency, reduce the power consumption and delays of neural networks implementation. In this thesis, we proposed three approximate multipliers for the mantissas multiplication, the first one is designed to reduce the number of calculations by putting one segment of the result to ‘1’ s. The second one is the Mitchell logarithmic multiplier and the third one is the logarithmic multiplier with a set-one adder to compensate for the negative error which is brought by the Mitchell multiplier. In order to evaluate these three multipliers, we are going to use YOLOv3, based on the open-source neural network framework which is called Darknet. This framework is dedicated to doing object recognition of images and we obtain the results after each execution

    An Optimized Architecture for CGA Operations and Its Application to a Simulated Robotic Arm

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    Conformal geometric algebra (CGA) is a new geometric computation tool that is attracting growing attention in many research fields, such as computer graphics, robotics, and computer vision. Regarding the robotic applications, new approaches based on CGA have been proposed to efficiently solve problems as the inverse kinematics and grasping of a robotic arm. The hardware acceleration of CGA operations is required to meet real-time performance requirements in embedded robotic platforms. In this paper, we present a novel embedded coprocessor for accelerating CGA operations in robotic tasks. Two robotic algorithms, namely, inverse kinematics and grasping of a human-arm-like kinematics chain, are used to prove the effectiveness of the proposed approach. The coprocessor natively supports the entire set of CGA operations including both basic operations (products, sums/differences, and unary operations) and complex operations as rigid body motion operations (reflections, rotations, translations, and dilations). The coprocessor prototype is implemented on the Xilinx ML510 development platform as a complete system-on-chip (SoC), integrating both a PowerPC processing core and a CGA coprocessing core on the same Xilinx Virtex-5 FPGA chip. Experimental results show speedups of 78x and 246x for inverse kinematics and grasping algorithms, respectively, with respect to the execution on the PowerPC processor

    Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

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    The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

    Applied Methuerstic computing

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    For decades, Applied Metaheuristic Computing (AMC) has been a prevailing optimization technique for tackling perplexing engineering and business problems, such as scheduling, routing, ordering, bin packing, assignment, facility layout planning, among others. This is partly because the classic exact methods are constrained with prior assumptions, and partly due to the heuristics being problem-dependent and lacking generalization. AMC, on the contrary, guides the course of low-level heuristics to search beyond the local optimality, which impairs the capability of traditional computation methods. This topic series has collected quality papers proposing cutting-edge methodology and innovative applications which drive the advances of AMC

    Design of an 8-bit Configurable CNN Hardware Accelerator for Audio and Image Classification

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    Picture yourself resting or attending a meeting in the back seat while your car is driving you home with all the privacy a driverless vehicle offers. Designing autonomous systems involves decoding environmental cues and making safe decisions. Convolution Neural Networks (CNNs) are the leading choices for computer vision tasks due to their high performance and scalability to pieces of hardware. They have long been run on Graphical Processing Units (GPUs) and Central Processing Units (CPUs). Yet, today, there is an urgent need to accelerate CNNs in low-power consumption hardware for real-time inference. This research aims to design a configurable hardware accelerator for 8-bit fixed point audio and image CNN models. An audio network is developed to classify environmental sounds from children playing in the streets, car horns, and sirens; an image network is designed to classify cars, lanes, road signs, traffic lights, and pedestrians. The two CNNs are quantized from a 32-bit floating-point to an 8-bit fixed-point format while maintaining high accuracy. The hardware accelerator is verified in SystemVerilog and compared to similar works

    Empirical multi-band characterization of propagation with modelling aspects for communictions

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    Diese Arbeit prĂ€sentiert eine empirische Untersuchung der Wellenausbreitung fĂŒr drahtlose Kommunikation im Millimeterwellen- und sub-THz-Band, wobei als Referenz das bereits bekannte und untersuchte sub-6-GHz-Band verwendet wird. Die großen verfĂŒgbaren Bandbreiten in diesen hohen FrequenzbĂ€ndern erlauben die Verwendung hoher instantaner Bandbreiten zur ErfĂŒllung der wesentlichen Anforderungen zukĂŒnftiger Mobilfunktechnologien (5G, “5G and beyond” und 6G). Aufgrund zunehmender Pfad- und Eindringverluste bei zunehmender TrĂ€gerfrequenz ist die resultierende Abdeckung dabei jedoch stark reduziert. Die entstehenden Pfadverluste können durch die Verwendung hochdirektiver Funkschnittstellen kompensiert werden, wodurch die resultierende Auflösung im Winkelbereich erhöht wird und die Notwendigkeit einer rĂ€umlichen Kenntnis der Systeme mit sich bringt: Woher kommt das Signal? DarĂŒber hinaus erhöhen grĂ¶ĂŸere Anwendungsbandbreiten die Auflösung im Zeitbereich, reduzieren das small-scale Fading und ermöglichen die Untersuchung innerhalb von Clustern von Mehrwegekomponenten. Daraus ergibt sich fĂŒr Kommunikationssysteme ein vorhersagbareres Bild im Winkel-, Zeit- und Polarisationsbereich, welches Eigenschaften sind, die in Kanalmodellen fĂŒr diese Frequenzen widergespiegelt werden mĂŒssen. Aus diesem Grund wurde in der vorliegenden Arbeit eine umfassende Charakterisierung der Wellenausbreitung durch simultane Multibandmessungen in den sub-6 GHz-, Millimeterwellen- und sub-THz-BĂ€ndern vorgestellt. Zu Beginn wurde die Eignung des simultanen Multiband-Messverfahrens zur Charakterisierung der Ausbreitung von Grenzwert-Leistungsprofilen und large-scale Parametern bewertet. Anschließend wurden wichtige Wellenausbreitungsaspekte fĂŒr die Ein- und Multibandkanalmodellierung innerhalb mehrerer SĂ€ulen der 5G-Technologie identifiziert und Erweiterungen zu verbreiteten rĂ€umlichen Kanalmodellen eingefĂŒhrt und bewertet, welche die oben genannten Systemaspekte abdecken.This thesis presents an empirical characterization of propagation for wireless communications at mm-waves and sub-THz, taking as a reference the already well known and studied sub-6 GHz band. The large blocks of free spectrum available at these high frequency bands makes them particularly suitable to provide the necessary instantaneous bandwidths to meet the requirements of future wireless technologies (5G, 5G and beyond, and 6G). However, isotropic path-loss and penetration-loss are larger with increasing carrier frequency, hence, coverage is severely reduced. Path-loss can be compensated with the utilization of highly directive radio-interfaces, which increases the resolution in the angular domain. Nonetheless, this emphasizes the need of spatial awareness of systems, making more relevant the question “where does the signal come from?” In addition, larger application bandwidths increase the resolution in the time domain, reducing small-scale fading and allowing to observe inside of clusters of multi-path components (MPCs). Consequently, communication systems have a more deterministic picture of the environment in the angular, time, and polarization domain, characteristics that need to be reflected in channel models for these frequencies. Therefore, in the present work we introduce an extensive characterization of propagation by intensive simultaneous multi-band measurements in the sub-6 GHz, mm-waves, and sub-THz bands. Firstly, the suitability of the simultaneous multi-band measurement procedure to characterize propagation from marginal power profiles and large-scale parameters (LSPs) has been evaluated. Then, key propagation aspects for single and multi-band channel modelling in several verticals of 5G have been identified, and extensions to popular spatial channel models (SCMs) covering the aforementioned system aspects have been introduced and evaluated

    A Solder-Defined Computer Architecture for Backdoor and Malware Resistance

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    This research is about securing control of those devices we most depend on for integrity and confidentiality. An emerging concern is that complex integrated circuits may be subject to exploitable defects or backdoors, and measures for inspection and audit of these chips are neither supported nor scalable. One approach for providing a “supply chain firewall” may be to forgo such components, and instead to build central processing units (CPUs) and other complex logic from simple, generic parts. This work investigates the capability and speed ceiling when open-source hardware methodologies are fused with maker-scale assembly tools and visible-scale final inspection. The author has designed, and demonstrated in simulation, a 36-bit CPU and protected memory subsystem that use only synchronous static random access memory (SRAM) and trivial glue logic integrated circuits as components. The design presently lacks preemptive multitasking, ability to load firmware into the SRAMs used as logic elements, and input/output. Strategies are presented for adding these missing subsystems, again using only SRAM and trivial glue logic. A load-store architecture is employed with four clock cycles per instruction. Simulations indicate that a clock speed of at least 64 MHz is probable, corresponding to 16 million instructions per second (16 MIPS), despite the architecture containing no microprocessors, field programmable gate arrays, programmable logic devices, application specific integrated circuits, or other purchased complex logic. The lower speed, larger size, higher power consumption, and higher cost of an “SRAM minicomputer,” compared to traditional microcontrollers, may be offset by the fully open architecture—hardware and firmware—along with more rigorous user control, reliability, transparency, and auditability of the system. SRAM logic is also particularly well suited for building arithmetic logic units, and can implement complex operations such as population count, a hash function for associative arrays, or a pseudorandom number generator with good statistical properties in as few as eight clock cycles per 36-bit word processed. 36-bit unsigned multiplication can be implemented in software in 47 instructions or fewer (188 clock cycles). A general theory is developed for fast SRAM parallel multipliers should they be needed
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