Designing and Performance Evaluation of Carry Select Adder

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better than the conventional CSA and CSA with BEC

Design of High Speed Carry Select Adder using Spurious Power Suppression Technique

Design of a compact, power efficient and high speed digital adder is one of the most extensive research area in VLSI Design. One of the goals is to increase speed which can be achieved by reducing the propagation delay. Carry Select adder (CSLA) is the most demanding adder which is utilized in data processing systems to achieve fast arithmetic results. Still there is scope for reducing the power consumption, area and delay in the existing designs of CSLAs. In this paper, an easy and competent technique has been used to achieve the same which includes designing of SPST based carry select adder comprising of detection unit and signed extension circuit. Adders being the most important building block of multiplier, will also enhance its performance

FPGA Implementation of Area, Delay and Power Efficient Carry Select Adder Architecture Design

The arithmetic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed. CSLA have great scope by reducing area, power consumption delay. However the regular CSLA is still area consuming due to dual RCA structure, for reducing the area The CSLA can be implemented by using single ripple carry adder (RCA) and BEC converter. In this paper, we present an innovative CSLA architecture which replaces the BEC using D-latch. Substantiation of proposed design is done through design and implementation of 16-bit adder circuit. Simulated result shows that the proposed architecture achieves two advantages in terms of area and delay. Implementation is done in Artix7 FPGA kit. For simulation Xilinx ISE 14.7 is used. DOI: 10.17762/ijritcc2321-8169.15051

IMPLEMENTATION OF CMOS ADDER FOR AREA & ENERGY EFFICIENT ARITHMETIC APPLICATIONS

The most fundamental arithmetic operation is addition which is used in a digital data path logic system. Arithmetic and logic units , Microprocessors ,etc. are some examples where we need to use arithmetic operations for processing data, for calculating addresses respectively .There are different architectures for building adder circuit .For example:1)carry look ahead adder(CLA),2)carry propagate adder(CPA),3)carry save adder(CSA), & 4)carry select adder(CSLA) . Among these different architectures CSLA is a particular way of implementing adder that performs addition rapidly and are used for faster addition in many data processing processors .From observation of the carry select adder architecture we can see that there is scope for modification in order to significantly minimize the area and power consumed by the circuit. In this work we are going to propose simple and efficient modification at gate-level structure in CSLA. Based on this 16-, 32-bit square root CSLA (SQRT CSLA) have been developed & compared with regular structure. The proposed architecture design has reduced area & power consumption compared to regular structure with slight increase in delay. The evaluation of the proposed design is done based on delay, area & power performance metrics. The results show that proposed CSLA design is better than regular SQRT CSLA

Design of 16-bit Heterogeneous Adder Architectures Using Different Homogeneous Adders

ABSTRACT: Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer

IMPLEMENTATION OF AREA-DELAY-POWER EFFICIENT CARRY SELECT ADDER USING CADENCE TOOL

In this transient, the logic operations concerned in conventional carry choose adder (CSLA) and binary to excess-1 device (BEC)-based CSLA square measure analyzed to review the information dependence and to spot redundant logic operations. We’ve got eliminated all the redundant logic operations gift within the standard CSLA and planned a replacement logic formulation for CSLA. Within the planned scheme, the carry chooses (CS) operation is scheduled before the calculation of final-sum that is totally different from the conventional approach. Bit patterns of 2 anticipating carry words (corresponding to can = zero and 1) and stuck can bits square measure used for logic optimization of atomic number 55 and generation units. Associate in nursing economical CSLA style is obtained victimization optimized logic units. The planned CSLA style involves considerably less space and delay than the recently planned BEC-based CSLA. Owing to the tiny carry output delay, the proposed CSLA style could be a sensible candidate for square root (SQRT) CSLA. A theoretical estimate shows that the planned SQRT-CSLA involves nearly thirty-fifth less area–delay–products (ADP) than the BEC-based SQRT-CSLA that is best among the existing SQRT-CSLA designs, on average, for various bit-widths. Carry choose Adder (CSLA) is one in every of the quickest adders utilized in several data-processing processors to perform quick arithmetic functions

EFFICIENT USAGE OF D LATCH FOR IMPLEMENTING A RELIABLE LOW POWER AREA CARRY SELECT ADDER

The Carry Select Adder is used in many systems to relieve the problem of carry propagation delay which is happen by independently generating multiple carries and to generate the sum then select a carry. Due to uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input However, the CSLA is not time efficient, then by the multiplexers the final sum and carry are selected. The basic idea of this work is to achieve high speed and low power consumption by use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA. At the same time to further reduce the power consumption, a new approach of CSLA with D LATCH is proposed in this project. In the proposed scheme, before the calculation of-final-sum the carry select that is specified as CS operation is scheduled. For logic optimization of Carry selection bit patterns of two anticipating carry words that is corresponding to cin = 0 and 1 and fixed cin bits are used. Using optimized logic units an efficient CSLA design is obtained. The proposed Carry Select Adder design involves significantly less area and power than the recently proposed BEC-based CSLA

LOW COMPLEXITY D LATCH BASED CSLA FOR SPEED CRITICAL APPLICATIONS

The Carry Select Adder is used in many systems to relieve the problem of carry propagation delay which is happen by independently generating multiple carries and to generate the sum then select a carry. Due to uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input However, the CSLA is not time efficient, then by the multiplexers the final sum and carry are selected. The basic idea of this work is to achieve high speed and low power consumption by use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA. At the same time to further reduce the power consumption, a new approach of CSLA with D LATCH is proposed in this project. In the proposed scheme, before the calculation of-final-sum the carry select that is specified as CS operation is scheduled. For logic optimization of Carry selection bit patterns of two anticipating carry words that is corresponding to cin = 0 and 1 and fixed cin bits are used. Using optimized logic units an efficient CSLA design is obtained. The proposed Carry Select Adder design involves significantly less area and power than the recently proposed BEC-based CSLA

16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies

High speed, low power, and area efficient adders and comparators continue to play a key role in hardware implementation of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This thesis demonstrates a unique custom designed 16-bit adder in 250-nm CMOS technology to obtain fast and power/area efficient features by combining CPL and CS logic. Comparing the results obtained for proposed 16-bit Linear CPL/CS adder with the BEC (Binary Excess-1 Code) based low power SQRT-CS adder, the delay is reduced by approximately one thirds, power is reduced by 19.2%, and the number of transistors is reduced by 23.4%. Also, new tree-based 64-bit static and dynamic digital comparators are presented in this thesis to perform high speed and low power operations. This tree-based architecture combines a new approach of designing dynamic comparator using a low duty cycle clock to reduce the short circuit power consumption in pre-charge (or pre-discharge) mode. This work also introduces a new sizing strategy and load balancing techniques to improve self-pipelining tendency of a tree based design. A resource sharing technique is also integrated in both static and dynamic comparator designs. At 1.2V power supply in CMOS 90nm technology, worst path delay and worst power are 374ps and 822µW, respectively for low cost static design with 1244 (768+476) transistors in total. 768 transistors are used for resource sharing. The proposed full and partially dynamic designs show superior power efficiency compared to recent state of art designs. The worst power consumptions at 5GHz and 25% (50ps) duty cycle clock for the 64-bit full and partially dynamic comparator designs are 5.00mW and 2.78mW, respectively. 769 (320+449) transistors includes 320 transistors for resource sharing, and 1217 (768+449) includes 768 transistors for resource sharing for full and partial dynamic comparators, respectively