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Parallel Programming for FPGAs
This book focuses on the use of algorithmic high-level synthesis (HLS) to
build application-specific FPGA systems. Our goal is to give the reader an
appreciation of the process of creating an optimized hardware design using HLS.
Although the details are, of necessity, different from parallel programming for
multicore processors or GPUs, many of the fundamental concepts are similar. For
example, designers must understand memory hierarchy and bandwidth, spatial and
temporal locality of reference, parallelism, and tradeoffs between computation
and storage. This book is a practical guide for anyone interested in building
FPGA systems. In a university environment, it is appropriate for advanced
undergraduate and graduate courses. At the same time, it is also useful for
practicing system designers and embedded programmers. The book assumes the
reader has a working knowledge of C/C++ and includes a significant amount of
sample code. In addition, we assume familiarity with basic computer
architecture concepts (pipelining, speedup, Amdahl's Law, etc.). A knowledge of
the RTL-based FPGA design flow is helpful, although not required