Compact Digital Predistortion for Multi-band and Wide-band RF Transmitters

This thesis is focusing on developing a compact digital predistortion (DPD) system which costs less DPD added power consumptions. It explores a new theory and techniques to relieve the requirement of the number of training samples and the sampling-rate of feedback ADCs in DPD systems. A new theory about the information carried by training samples is introduced. It connects the generalized error of the DPD estimation algorithm with the statistical properties of modulated signals. Secondly, based on the proposed theory, this work introduces a compressed sample selection method to reduce the number of training samples by only selecting the minimal samples which satisfy the foreknown probability information. The number of training samples and complex multiplication operations required for coefficients estimation can be reduced by more than ten times without additional calculation resource. Thirdly, based on the proposed theory, this thesis proves that theoretically a DPD system using memory polynomial based behavioural modes and least-square (LS) based algorithms can be performed with any sampling-rate of feedback samples. The principle, implementation and practical concerns of the undersampling DPD which uses lower sampling-rate ADC are then introduced. Finally, the observation bandwidth of DPD systems can be extended by the proposed multi-rate track-and-hold circuits with the associated algorithm. By addressing several parameters of ADC and corresponding DPD algorithm, multi-GHz observation bandwidth using only a 61.44MHz ADC is achieved, and demonstrated the satisfactory linearization performance of multi-band and continued wideband RF transmitter applications via extensive experimental tests

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

Characterization and modelling of software defined radio front-ends

Doutoramento em Engenharia ElectrotécnicaO presente trabalho tem por objectivo estudar a caracterização e modelação de arquitecturas de rádio frequência para aplicações em rádios definidos por software e rádios cognitivos. O constante aparecimento no mercado de novos padrões e tecnologias para comunicações sem fios têm levantado algumas limitações à implementação de transceptores rádio de banda larga. Para além disso, o uso de sistemas reconfiguráveis e adaptáveis baseados no conceito de rádio definido por software e rádio cognitivo assegurará a evolução para a próxima geração de comunicações sem fios. A ideia base desta tese passa por resolver alguns problemas em aberto e propor avanços relevantes, tirando para isso partido das capacidades providenciadas pelos processadores digitais de sinal de forma a melhorar o desempenho global dos sistemas propostos. Inicialmente, serão abordadas várias estratégias para a implementação e projecto de transceptores rádio, concentrando-se sempre na aplicabilidade específica a sistemas de rádio definido por software e rádio cognitivo. Serão também discutidas soluções actuais de instrumentação capaz de caracterizar um dispositivo que opere simultaneamente nos domínios analógico e digital, bem como, os próximos passos nesta área de caracterização e modelação. Além disso, iremos apresentar novos formatos de modelos comportamentais construídos especificamente para a descrição e caracterização não-linear de receptores de amostragem passa-banda, bem como, para sistemas nãolineares que utilizem sinais multi-portadora. Será apresentada uma nova arquitectura suportada na avaliação estatística dos sinais rádio que permite aumentar a gama dinâmica do receptor em situações de multi-portadora. Da mesma forma, será apresentada uma técnica de maximização da largura de banda de recepção baseada na utilização do receptor de amostragem passa-banda no formato complexo. Finalmente, importa referir que todas as arquitecturas propostas serão acompanhadas por uma introdução teórica e simulações, sempre que possível, sendo após isto validadas experimentalmente por protótipos laboratoriais.This work investigates the characterization and modeling of radio frequency front-ends for software defined radio and cognitive radio applications. The emergence of new standards and technologies in the wireless communications market are raising several issues to the implementation of wideband transceiver systems. Also, reconfigurable and adaptable systems based on software defined and cognitive radio models are paving the way for the next generation of wireless systems. In this doctoral thesis the fundamental idea is to address the particular open issues and propose appropriate advancements by exploring and taking profit from new capabilities of digital signal processors in a way to improve the overall performance of the novel schemes. Receiver and transmitter strategies for radio communications are summarized by concentrating on the usability for software defined radio and cognitive radio systems. Available instrumentation and next steps for analog and digital radio frequency hardware characterization is also discussed. Wideband behavioral model formats are proposed for nonlinear description and characterization of bandpass sampling receivers, as well as, for multi-carrier nonlinear systems operation. The proposed models share a great flexibility and have the freedom to be simply expanded to other fields. A new design for receiver dynamic range improvement in multi-carrier scenarios is proposed, which is supported on the useful wireless signals statistical evaluation. Additionally, receiver-side bandwidth maximization based on higher-order bandpass sampling approaches is evaluated. All the proposed designs and modeling strategies are accompanied by theoretical backgrounds and simulations whenever possible, being then experimentally validated by laboratory prototypes

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

ワイヤレス通信のための先進的な信号処理技術を用いた非線形補償法の研究

The inherit nonlinearity in analogue front-ends of transmitters and receivers have had primary impact on the overall performance of the wireless communication systems, as it gives arise of substantial distortion when transmitting and processing signals with such circuits. Therefore, the nonlinear compensation (linearization) techniques become essential to suppress the distortion to an acceptable extent in order to ensure sufficient low bit error rate. Furthermore, the increasing demands on higher data rate and ubiquitous interoperability between various multi-coverage protocols are two of the most important features of the contemporary communication system. The former demand pushes the communication system to use wider bandwidth and the latter one brings up severe coexistence problems. Having fully considered the problems raised above, the work in this Ph.D. thesis carries out extensive researches on the nonlinear compensations utilizing advanced digital signal processing techniques. The motivation behind this is to push more processing tasks to the digital domain, as it can potentially cut down the bill of materials (BOM) costs paid for the off-chip devices and reduce practical implementation difficulties. The work here is carried out using three approaches: numerical analysis & computer simulations; experimental tests using commercial instruments; actual implementation with FPGA. The primary contributions for this thesis are summarized as the following three points: 1) An adaptive digital predistortion (DPD) with fast convergence rate and low complexity for multi-carrier GSM system is presented. Albeit a legacy system, the GSM, however, has a very strict requirement on the out-of-band emission, thus it represents a much more difficult hurdle for DPD application. It is successfully implemented in an FPGA without using any other auxiliary processor. A simplified multiplier-free NLMS algorithm, especially suitable for FPGA implementation, for fast adapting the LUT is proposed. Many design methodologies and practical implementation issues are discussed in details. Experimental results have shown that the DPD performed robustly when it is involved in the multichannel transmitter. 2) The next generation system (5G) will unquestionably use wider bandwidth to support higher throughput, which poses stringent needs for using high-speed data converters. Herein the analog-to-digital converter (ADC) tends to be the most expensive single device in the whole transmitter/receiver systems. Therefore, conventional DPD utilizing high-speed ADC becomes unaffordable, especially for small base stations (micro, pico and femto). A digital predistortion technique utilizing spectral extrapolation is proposed in this thesis, wherein with band-limited feedback signal, the requirement on ADC speed can be significantly released. Experimental results have validated the feasibility of the proposed technique for coping with band-limited feedback signal. It has been shown that adequate linearization performance can be achieved even if the acquisition bandwidth is less than the original signal bandwidth. The experimental results obtained by using LTE-Advanced signal of 320 MHz bandwidth are quite satisfactory, and to the authors’ knowledge, this is the first high-performance wideband DPD ever been reported. 3) To address the predicament that mobile operators do not have enough contiguous usable bandwidth, carrier aggregation (CA) technique is developed and imported into 4G LTE-Advanced. This pushes the utilization of concurrent dual-band transmitter/receiver, which reduces the hardware expense by using a single front-end. Compensation techniques for the respective concurrent dual-band transmitter and receiver front-ends are proposed to combat the inter-band modulation distortion, and simultaneously reduce the distortion for the both lower-side band and upper-side band signals.電気通信大学201

Design and implementation of a wideband sigma delta ADC

Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTƩ∆M), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications. The objective of this thesis is to design and implement a wideband CTƩ∆M for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTƩ∆M, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADC’s sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB. This thesis focuses on the design and implementation of the CTƩ∆M, building upon the principles of a discrete time Ʃ∆ modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTƩ∆ modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTƩ∆ modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTƩ∆M. The CTƩ∆Ms employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulator’s performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. Tiivistelmä. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistä tärkeämmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnän kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTƩ∆M), joissa käytetään ylinäytteistystä ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun. Tämän työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjärjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTƩ∆M, jolla on 15MHz:n signaalikaistanleveys. Ylinäytteistyssuhde on 25 ja AD muuntimen näytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR). Tämä työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Ʃ∆-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmä esitetään yksityiskohtaisesti, ja vaatimusten täyttyminen varmistetaan “top-down” -suunnitteluperiaatteella. Liitteenä on kertoimien laskemiseen käytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkän silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentä -DA muunninta. Viivekompensointipolkua käyttämällä modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. Lisäksi FIR takaisinkytkentä -DA-muuntimen käyttö pienentää kellojitteriherkkyyttä, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyä ja luotettavuutta. Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty peräkkäin integraattoreita myötäkytkentärakenteella (CIFF) ja toisessa sekä myötä- että takaisinkytkentärakenteella (CIFF-B). Päähuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa käyttäen 0.8 voltin käyttöjännitettä. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. Lisäksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin