Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures

Conception et réalisation d'un outil d'exploration architecturale de la hiérarchie de mémoire d'un système sur puce afin d'optimiser la performance de la plateforme logicielle

Les systèmes embarqués d'aujourd'hui -- Systèmes sur puce : hiérarchie mémoire, logiciel et optimisation -- Hiérarchie mémoire -- Structure d'un logiciel compilé -- Optimisation de la hiérarchie -- Environnement de simulation space -- Mise à jour de la plateforme de simulation space -- Plateforme microblaze -- Environnement de simulation space -- Mise à jour des composantes -- Outil de traçage d'exécution -- Memoryoptimizer : optimisation de la hiérarchie mémoire -- Flot d'exécution -- Partitionnement de mémoire -- Optimisation de la mémoire cache -- Analyse, performances et discussion -- Méthodologie d'analyse des performances -- Résultats de l'exploration architecturale -- Efficacité des algorithmes de compression de traces -- Extensibilité à d'autres processeurs/plateformes de simulation -- Comparaison avec d'autres travaux -- Rencontre des requis

Architectural Exploration and Optimization of Local Memory in Embedded Systems*

Embedded processor-based systems allow for the tai-Zoring of the on-chip memory architecture based on appiicaiion-specific requirements. We present an analytical strategy for exploring the on-chip memory archifecture for a given application, based on a memory performance esti-mation scheme. The anaiyrical technique has fhe important advantage of enabling a fast evaluafion of candidate mem-ory architectures in the early stages of system design. Our experiments demonslrare that our estimations closelyfo&w the actual simrrlared performunce, at significantly reduced run times. 1