Applying Formal Verification with Protocol Compiler

This paper presents a practical methodology for the application of formal verification to the industrial design environment "Protocol Compiler". Our verification flow is to first create a testbench and simulate the design. Then we modify the testbench and perform a formal verification technique called assertion checking. The examples are taken from the networking arena. The first is a simplified RS232 transceiver, the second a pipelined FIFO-like buffer written in Verilog. We show that assertion checking fits well into the design flow and is easy to use within Protocol Compiler. 1

Applying Formal Verification with Protocol Compiler

This paper gives two examples how to verify designs with Protocol Compiler. Our verification flow is to first create a testbench and simulate the design. Then we modify the testbench and perform a formal verification technique called assertion checking. The examples are taken from the networking arena. The first is a simplified RS232 transceiver, the second a pipelined FIFO-like buffer. We find that assertion checking fits well into the design flow and is easy to use within Protocol Compiler. 1. Introduction Recently usage of complex controller designs like ATM, Sonet, SDH, etc. as well as their complexity has increased and due to Moore's law we can expect this to continue. Much design time is spent verifying the design and nearly all of it is done by simulation. But, as the complexity of the design increases, simulation loses its sufficiency. To guarantee correctness of complex designs, formal verification (FV) techniques are a useful supplement to simulation. Unfortunately, forma..