A thermal simulation process based on electrical modeling for complex interconnect, packaging, and 3DI structures

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost. © 2006 IEEE.published_or_final_versio

Microbridge Formation for Low Resistance Interline Connection Using Pulsed Laser Techniques

MakeLink® technology has been applied in many semiconductor devices to achieve high performance. Sometimes one-type-link design doesn't make desirous links for all IC manufacturing processes. In this work, four new structures, called microbridge, were designed to form all types of link. Laser processing experiments were performed to verify the designs. The results show that two-lower-level-metal-line design has higher performance (low link resistance), higher productivity (broad energy window), and higher yield than the three-lower-level-metal-line design. Therefore, it can be considered as the optimal design from the processing point of view. Two-lower-level-metal-line with lateral gap structure provides better scalability and it can be used in next generation ICs. If high-speed is the primary concern, an advanced-lateral structure is best, corresponding to its much lower resistance. The reliability tests indicate that the median-times-to-failure of all test structures are greater than nine years in operating condition, presenting reasonable lifetimes for integrated circuits used in the market. A two-dimensional finite element plane models for microbridge formation is developed. Results are compared to the experiments with process windows to present their consistence. The model allowed for using different geometric parameters and metal-dielectric combinations optimizing the design. An optimal design diagram for the Al/SiO2 system is created to provide the designer with criteria to avoid the failure of structure. Trade-off requirements, such as process window and structure size, are also provided. Guidelines are obtained for the Cu/Low-K dielectric system

Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Thermal Investigations Of Flip Chip Microelectronic Package With Non-Uniform Power Distribution [TK7874. G614 2004 f rb] [Microfiche 7607].

Arah aliran pempakejan sistem-sistem dan subsistem mikroelektronik adalah kearah pengurangan saiz dan peningkatan prestasi, di mana kedua-duanya menyumbang kepada peningkatan kadar penjanaan haba. The trend in packaging microelectronic systems and subsystems has been to reduce size and increase performance, both of which contribute to increase heat generation

Electrical characterization of plasma-enhanced Cvd silicon nitride dielectric on copper

In this work, a novel metal-insulator-metal (MIM) capacitor process is introduced and integrated in a Copper Interconnect technology, whose smallest feature size is 0.18mum process, which has good yield, reliability and repeatability. The MIM uses a one-photomask process and hence is termed as the Low-cost-integration (LCI) MIM. The LCI MIM uses copper as the bottom electrode, plasma enhanced silicon nitride as the dielectric, and Tantalum nitride as the top electrode. The target capacitance density is 1.5fF/mum2. The target leakage current is 1e-7A/cm2 at 3.3V at 125°C. The maximum operating voltages that the MIM is designed for is 5V. The voltage linearity is desired to be less than 100ppm/v; The purpose of the study is to determine the feasibility of integrating the low-cost-integration (LCI) MIM capacitor and to characterize the device to ensure that it meets the above mentioned target values for the various parameters. This is done by electrically characterizing the capacitor for the capacitance change with voltage, the leakage current at accelerated voltages and the time-dependent-dielectric breakdown (TDDB) under various electric fields. (Abstract shortened by UMI.)

PECVD low stress silicon nitride analysis and optimization for the fabrication of CMUT devices

Two technological options to achieve a high deposition rate, low stress plasma-enhanced chemical vapor deposition (PECVD) silicon nitride to be used in capacitive micromachined ultrasonic transducers (CMUT) fabrication are investigated and presented. Both options are developed and implemented on standard production line PECVD equipment in the framework of a CMUT technology transfer from R & D to production. A tradeoff between deposition rate, residual stress and electrical properties is showed. The first option consists in a double layer of silicon nitride with a relatively high deposition rate of ~100 nm min−1 and low compressive residual stress, which is suitable for the fabrication of the thick nitride layer used as a mechanical support of the CMUTs. The second option involves the use of a mixed frequency low-stress silicon nitride with outstanding electrical insulation capability, providing improved mechanical and electrical integrity of the CMUT active layers. The behavior of the nitride is analyzed as a function of deposition parameters and subsequent annealing. The nitride layer characterization is reported in terms of interfaces density influence on residual stress, refractive index, deposition rate, and thickness variation both as deposited and after thermal treatment. A sweet spot for stress stability is identified at an interfaces density of 0.1 nm−1, yielding 87 MPa residual stress after annealing. A complete CMUT device fabrication is reported using the optimized nitrides. The CMUT performance is tested, demonstrating full functionality in ultrasound imaging applications and an overall performance improvement with respect to previous devices fabricated with non-optimized silicon nitride