Onboard Experiment Data Support Facility (OEDSF): Conceptual design study

The Onboard Experimental Data Support Facility (OEDSF) is an inflight data processor based on a totally new architecture specifically developed to cost-effectively process the data of Shuttle payloads sensors. Processing data onboard fills the following needs: (1) reduction of data bulk by conversion to information (2)quick-look for evaluation, interactive operation, etc. (3) real-time computation of engineering representation of sensed phenomena. For example: Value of backscatter coefficient (sigma) of a scatterometer as a function of latitude and longitude (4) exploitation of the real-time availability of ancillary data, thereby obviating the need for time-tagging, recording, and recorrelation and (5) providing data or information immediately usable by the experimenter or user. The OEDSF is made up of modular and cascadable matrix processors. Each matrix has been sized to process the data of a full typical shuttle payload. Cost analyses indicate that significant savings are realized by processing data with the OEDSF compared with conventional ground facilities

A framework for FPGA functional units in high performance computing

FPGAs make it practical to speed up a program by defining hardware functional units that perform calculations faster than can be achieved in software. Specialised digital circuits avoid the overhead of executing sequences of instructions, and they make available the massive parallelism of the components. The FPGA operates as a coprocessor controlled by a conventional computer. An application that combines software with hardware in this way needs an interface between a communications port to the processor and the signals connected to the functional units. We present a framework that supports the design of such systems. The framework consists of a generic controller circuit defined in VHDL that can be configured by the user according to the needs of the functional units and the I/O channel. The controller contains a register file and a pipelined programmable register transfer machine, and it supports the design of both stateless and stateful functional units. Two examples are described: the implementation of a set of basic stateless arithmetic functional units, and the implementation of a stateful algorithm that exploits circuit parallelism

Research in nonlinear structural and solid mechanics

Recent and projected advances in applied mechanics, numerical analysis, computer hardware and engineering software, and their impact on modeling and solution techniques in nonlinear structural and solid mechanics are discussed. The fields covered are rapidly changing and are strongly impacted by current and projected advances in computer hardware. To foster effective development of the technology perceptions on computing systems and nonlinear analysis software systems are presented

Embedded Firmware Solutions

Computer scienc

The formal verification of generic interpreters

The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does

Formal Verification of the AAMP-FV Microcode

This report describes the experiences of Collins Avionics & Communications and SRI International in formally specifying and verifying the microcode in a Rockwell proprietary microprocessor, the AAMP-FV, using the PVS verification system. This project built extensively on earlier experiences using PVS to verify the microcode in the AAMP5, a complex, pipelined microprocessor designed for use in avionics displays and global positioning systems. While the AAMP5 experiment demonstrated the technical feasibility of formal verification of microcode, the steep learning curve encountered left unanswered the question of whether it could be performed at reasonable cost. The AAMP-FV project was conducted to determine whether the experience gained on the AAMP5 project could be used to make formal verification of microcode cost effective for safety-critical and high volume devices