Analyzing and Improving Delay Defect Tolerance in Pipelined Combinational Circuits

In this paper, we consider the problems of identification of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modification to improve the circuit's tolerance of delay faults. The results assume purely combinational logic, and fixed gate delays calculated under floating delay mode. 1 Introduction In this section, an overview is provided for the component sensitivity criteria used in determining delay fault sensitivity and improving delay fault tolerance. In section 2 we introduce the notation and definitions to be used. Section 3 contains discussion of the use of long sensitizable paths and short topological paths to determine circuit clock settings. In section 4, the path lengths and clock settings are used to identify component sensitivity to delay increases and delay decreases, and in sections 5 and 6, the use of component sensitivity is discussed as a guide to improving global delay defect tolerance using gate resizing. Finally in section 7 the..