Dual material gate field effect transistor (DMG-FET)

Improving performance and suppressing short channel effects are two of the most important issues in present field effect transistors development. Hence, high performance and long channel like behaviors are essential requirements for short channel FETs. This dissertation focuses on new ways to achieve these significant goals. A new field effect transistor - dual material gate FET (DMG-FET) - is presented for the first time. The unique feature of the DMG-FET is its gate which consists of two laterally contacting gate materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that charge carriers are accelerated more rapidly in the channel and the channel potential near the source is screened from the drain bias after saturation. Using HFET as a vehicle, it is shown that the drive current and transconductance in DMG-FET are therefore substantially enhanced as compared to conventional FET. Moreover, it is observed that the short channel effects such as channel length modulation, DIBL and hot-carrier effect are significantly suppressed. Numerical simulations are employed to investigate the new device structure and related phenomenon. A simple and practical DMG-HFET fabrication process has been developed. The proposed DMG-HFET is thus realized for the first time. Experimental results exhibit improved characteristics as the simulation results predicted

Modeling and simulation of strained graprene nanoribbon field effect transistor

Stretching technique used in material fundamental is not a new technology. It has been adopted in silicon industry to overcome the limitations arisen by scaling down the size of the conventional metal oxide semiconductor Field Effect Transistor (FET). This technique is known as strain technology. As the semiconductor industry grows in their maturity, the replacement of strained silicon with another material offering a higher potential quasi-ballistic-carrier velocity and higher mobility is importance. Recent enlisted superior material is quasi-one dimensional Graphene NanoRibbons (GNR). GNR is the most promising material for future nanoelectronic that inherited most properties from graphene and Carbon NanoTube (CNT) itself. To characterize the effect made by strain technology in silicon, an analytical model of strained GNRFET is presented in this work to analyse the suitability of this material for future FET. This works presents a simple model of current-voltage characteristic in the function of strain for different widths. By using a tight-binding approximation and analytical solution, the strained GNR bandstructure, density of states and carrier statistic are presented. Further observation on their carrier transport and their current-voltage characteristic is also investigated and presented in this research. It is found in this research that strain gives significant effect according to different width groups. It is successful in tailoring the energy gap and linearly changing the carrier statistic and carrier transport. In terms of physical and electrical performance, strained 3m+1 GNR is found to be a good material for future FET with enhanced mobility due to the energy gap alteration by strain. Strained GNRFET also was found to be 55mV/dec in subthreshold slope, which is smaller than normal GNRFET, which means the transistor has faster switching. Besides, the currentvoltage characteristic is reported to have delayed saturation region compared to published model due to the different in quantum effect consideration

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future