Optimization of ring oscillators

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de ComputadoresVoltage Controlled Oscillators (VCOs) are from all the building blocks of a PLL, those whose implementation is more critical, since the quality of the signal depends on its performance. The VCOs can be implemented based on LC oscillators or ring oscillators. The ring oscillators, despite of being worst when it comes to manners of phase noise, they are rather used due to lower power consumption, wider tuning range and occupying less area. Despite the fact that VCOs are widely used in last years, their designed is still a problem hard to deal with, since the ring oscillators circuits must satisfy some specifications such as area, power, speed and noise. The work proposed in this thesis aims at the development of an environment for automatic scaling of voltage-controlled oscillators with ring topology. In this work it was considered a design methodology based optimization using an analytical model of the oscillator. The oscillator model is based on the EKV model for the characterization of the transistors so as to ensure its applicability to submicron dimensions technologies. The work took place according to the following phases: - Study of ring oscillators and models proposed in the literature - Evaluation of the limitations of existing models and proposed use of EKV model. - Automatic determination of the parameters of the EKV model for UMC130 technology - Development of an analytic model for characterizing the VCO with predefined delay cell. - Use of optimization techniques for automatic sizing of the VCO

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThis thesis proposes a study of three different RC oscillators, two relaxation and a ring oscillator. All the circuits are implemented using UMC 130 nm CMOS technology with a supply voltage of 1.2 V. We present a wideband MOS current/voltage controlled quadrature oscillator constituted by two multivibrators. Two different forms of coupling named, soft (traditional)and hard (proposed) are differentiated and investigated. It is found that hard coupling reduces the quadrature error and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling. The behaviour of the singular and coupled multivibrators is investigated, when an external synchronizing harmonic is applied. We introduce a new RC relaxation oscillator with pulse self biasing, to reduce power consumption, and with harmonic ltering and resistor feedback, to reduce phase-noise. The designed circuit has a very low phase-noise, -132.6 dBc/Hz @ 10 MHz offset, and the power consumption is only 1 mW, which leads to a gure of merit (FOM) of -159.1 dBc/Hz. The nal circuit is a two integrator fully implemented in CMOS technology, with low power consumption. The respective layout is made and occupies a total area of5.856x10-3 mm2, post-layout simulation is also done

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

Frequency domain steady-state simulation of oscillators

The focus of this work is on developing algorithms for frequency domain steady-state analysis of oscillators. Convergence problems associated with the frequency domain harmonic balance simulation of oscillators have been examined. Globally convergent homotopy methods have been combined with the harmonic balance method for robust high-Q oscillator simulation. Various homotopy options are evaluated leading to an algorithm that is applicable to a wide variety of oscillator circuits. Two new approaches have also been developed for the simulation of ring oscillators using the harmonic balance method. These include a single-delay cell method and a multiple-probe method. The new methods that have been proposed are robust compared to traditional methods and readily converge for a wide range of single-ended and differential oscillators. They enable harmonic balance simulation of “difficult-to-converge” oscillator circuits

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort