Rosenstiel: Analysis of the XC6000 Architecture for Embedded System Design

Novel FPGA architectures combined with new implementation methods influence the widespread area of embedded system design. Current research results based on the Global Run Time Reconfiguration (RTR) method show improvements to the functional density of up to 500 % incontrast to the widely used Compile Time Reconfiguration (CTR) method. In addition, the RTR method applied to a partial reconfigurable architecture, like Xilinx XC6000, promises further enhancements. This paper analyses different implementation methods in order to exploit the resources of specific FPGA architectures. The development of an ATM diagnostic monitor serves as a realistic application to analyse these methods. We will analyse the differences between the XC4000E/EX and XC6000 FPGA architecture, based on their use of the same CTR implementation method. Additionally, applying Local RTR to XC6000 leads to a further benefit of about 20 % in contrast to the CTR method. The evaluation process is based on the FZI internal rapid prototyping environment, which is best suited for sophisticated ATM applications.