Analysis and Design of an Array of Two Differential Oscillators Coupled Through a Resistive Network

International audienceThis paper considers the analysis and the design of an array of two NMOS differential oscillators coupled through a resistor. A new writing of the nonlinear equations proposed by R. York to describe the oscillators' locked states but limited for the specific case of a resistive coupling is presented. The new system permits the calculation of the free-running frequencies of the oscillators when a specific phase shift is desired. This has led to the modeling of the two coupled NMOS differential oscillators as two coupled differential Van der Pol oscillators, with a resistive coupling network. A good agreement between the circuit, the model and the theory was found, giving some design considerations for a network of two differential oscillators coupled through one resistor

A CAD Tool for an Array of Differential Oscillators Coupled Through a Broadband Network

International audienceA new expression of the equations describing the locked states of two oscillators coupled through a resistor is presented in this article. This theory has led to the elaboration of a CAD tool which provides, in a short simulation time, the frequency locking region of two coupled differential oscillator

Design and Implementation of A 6-GHz Array of Four Differential VCOs Coupled Through a Resistive Network

International audienceThis paper presents the design and the implementation of a fully monolithic coupled-oscillator array, operating at 6 GHz with close to zero coupling phase, in 0.25 μm BICMOS SiGe process. This array is made of four LC-NMOS differential VCOs coupled through a resistor. The single LC-NMOS VCO structure is designed and optimized in terms of phase noise with a graphical optimization approach while satisfying design constraints. At 2.5 V power supply voltage, and a power dissipation of only 125 mW, the coupled oscillators array features a simulated phase noise of -127.3 dBc/Hz at 1 MHz frequency offset from a 6 GHz carrier, giving a simulated phase progression that was continuously variable over the range -64° < Δphi <64 ° and -116° < Δphi < 116°. This constant phase progression can be established by slightly detuning the peripheral array elements, while maintaining mutual synchronization