Quad-Core RSA Processor with Countermeasure Against Power Analysis Attacks

Rivest-Shamir-Adleman (RSA) cryptosystem uses modular multiplication for encryption and decryption. So, performance of RSA can be drastically improved by optimizing modular multiplication. This paper proposes a new parallel, high-radix Montgomery multiplier for 1024 bits multi-core RSA processor. Each computation step operates in radix 4. The computation speed is increased by more than 4 times. We also implement a True Random Number Generator based resilience block to protect the coprocessor against power attacks

Design and Architecture of Hardware-based Random Function Security Primitives

In recent years, security has grown into a critical issue in modern information systems. Electronic hardware security, in particular, has emerged as one of the most serious challenges due to electronic devices penetrating every aspect of our society. Furthermore, due to the trend in globalization, system integrators have had to deal with integrated circuit (IC)/intellectual property (IP) counterfeiting more than ever. These counterfeit hardware issues counterfeit hardware that have driven the need for more secure chip authentication, since traditional ID or key storage have been demonstrated to be vulnerable to various kinds of attacks. In addition, due to the need for highly secure electronic information systems, almost every important and valuable document or piece of data is stored/transferred in some type of encrypted form to prevent attackers from compromising privacy or stealing information for nefarious uses. High entropy random numbers from physical sources are a critical component in authentication and encryption processes within secure systems. Secure encryption is dependent on sources of truly random numbers for generating keys, and there is a need for an on chip random number generator to achieve adequate security. Furthermore, the Internet of Things (IoT) adopts a large number of these hardware based security and prevention solutions in order to securely exchange data in resource-efficient manner. Note that due to the nature of IoT systems, these networked devices are particularly vulnerable to attacks that involve physical manipulations. In this work, we have developed several methodologies of hardware based random functions in order to address the issues and enhance the security and trust of ICs. The methodologies proposed in this thesis include: a novel DRAM-based intrinsic Physical Unclonable Function (PUF) for system-level security and authentication along with analysis of the impact of various environmental conditions, particularly silicon aging; a DRAM remanence based True Random Number Generation (TRNG) to produce random sequences with a very low-cost overhead; a DRAM TRNG model using its startup value behavior for creating random bit streams; an efficient power-supply noise based TRNG model for generating an infinite number of random bits which has been evaluated as a cost effective technique; architectures and hardware security solutions for the Internet of Things (IoT) environment. Since IoT devices are heavily resource-constrained, our proposed designs can alleviate the concerns and issues of establishing trustworthy and secure systems in an efficient and low-cost manner