An improved fault mitigation strategy for CUDA Fermi GPUs

High computation is a predominant requirement in many applications. In this field, Graphic Processing Units (GPUs) are more and more adopted. Low prices and high parallelism let GPUs be attractive, even in safety critical applications. Nonetheless, new methodologies must be studied and developed to increase the dependability of GPUs. This paper presents an improved fault mitigation strategy against permanent faults for CUDA Fermi GPUs. The proposed approach exploits the reverse engineering of the block scheduling policy in CUDA Fermi GPUs in order to minimize the fault mitigation timing overhead. The graceful performance degradation achieved by the proposed technique outperforms multithreaded CPU implementations and other fault mitigation strategies for CUDA GPU, even in presence of multiple permanent faults

An Improved Approach to Fault Tolerant Rank Order Filtering on a SIMD Mesh Processor

This paper presents an approach for the fault tolerant computation of the rank order fi ltering on a SIMD (Single Instruction Multiple Data) mesh processor, such as the MasPar. The proposed approachimprovesover a previous approach [ 12] intwo respects: bychanging the datadependency in the execution of the rankorder fi ltering, a new algorithmwith constantexecution time complexity can be designed; and by introducing a dependency for the rank values of faulty PEs as computed by neighboring (fault free) processing elements (PEs), a lower distortion can be achieved for enhancement of the image. 1 Introduction Image andsignalprocessing have beenwidelyadvocatedaspossible applicationareas forparallel computationusing homogeneoussystems, suchas the meshand the hypercube [7, 14, 15]. However, the use of these systems in highly reliable applications as well as the difficulty in manufacturing a fullyembeddedsystemusing highdensityand large areatechnologies, warrantthe use of defect/fault toleran..