An experimental analysis of the effectiveness of the circular self-test path technique

* The paper analyzes the effectiveness of the Circular Self-Test Path technique from an experimental point of view. Several fault simulation experiments have been performed on the ISCAS89 benchmark set as well as on a set of real circuits: in contrast to the theoretical analysis proposed in [PKKa92], a very high Fault Coverage has been attained with a limited number of clock cycles, provided that the circuit does not enter a loop. This danger can not be avoided even if clever strategies for Flip-Flops ordering, aimed at reducing the functional adjacency, are adopted; the effects of carefully choosing the initial state are investigated and an approach based on Formal Verification techniques is proposed. 1. Introduction BIST techniques are nowadays widely used for testing both whole devices and embedded portions like ROMs, RAMs, combinational chunks of logic and FSMs. A BIST approach to sequential circuits testing has been proposed and deeply analyzed from a theoretical point of view ..