1 research outputs found
Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes
In this paper we propose the construction of Spatially Coupled Low-Density
Parity-Check (SC-LDPC) codes using a periodic time-variant Quasi-Cyclic (QC)
algorithm. The QC based approach is optimized to obtain memory efficiency in
storing the parity-check matrix in the decoders. A hardware model of the
parity-check storage units has been designed for Xilinx FPGA to compare the
logic and memory requirements for various approaches. It is shown that the
proposed QC SC-LDPC code (with optimization) can be stored with reasonable
logic resources and without the need of block memory in the FPGA. In addition,
a significant improvement in the processing speed is also achieved.Comment: 6 pages, 8 figures, 1 table, submitted to journa