Energy efficiency of error correction on wireless systems

Since high error rates are inevitable to the wireless environment, energy-efficient error-control is an important issue for mobile computing systems. We have studied the energy efficiency of two different error correction mechanisms and have measured the efficiency of an implementation in software. We show that it is not sufficient to concentrate on the energy efficiency of error control mechanisms only, but the required extra energy consumed by the wireless interface should be incorporated as well. A model is presented that can be used to determine an energy-efficient error correction scheme of a minimal system consisting of a general purpose processor and a wireless interface. As an example we have determined these error correction parameters on two systems with a WaveLAN interfac

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient

Performance analysis of a hybrid ARQ system in half duplex transmission at 2400 BPS

Hybrid ARQ/FEC protocols have been proposed to provide high data link integrities whilst keeping at the same time a high mean throughput rate. Nevertheless, hybrid ARQ strategies offer a lot of choices and none of them can be considered the optimum in any case. Three alternative protocol strategies using BCH codes are evaluated and the HF channel models used for the tests are discussed.Peer ReviewedPostprint (published version

Havens: Explicit Reliable Memory Regions for HPC Applications

Supporting error resilience in future exascale-class supercomputing systems is a critical challenge. Due to transistor scaling trends and increasing memory density, scientific simulations are expected to experience more interruptions caused by transient errors in the system memory. Existing hardware-based detection and recovery techniques will be inadequate to manage the presence of high memory fault rates. In this paper we propose a partial memory protection scheme based on region-based memory management. We define the concept of regions called havens that provide fault protection for program objects. We provide reliability for the regions through a software-based parity protection mechanism. Our approach enables critical program objects to be placed in these havens. The fault coverage provided by our approach is application agnostic, unlike algorithm-based fault tolerance techniques.Comment: 2016 IEEE High Performance Extreme Computing Conference (HPEC '16), September 2016, Waltham, MA, US