247 research outputs found
Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers
A massive gap exists between current quantum computing (QC) prototypes, and
the size and scale required for many proposed QC algorithms. Current QC
implementations are prone to noise and variability which affect their
reliability, and yet with less than 80 quantum bits (qubits) total, they are
too resource-constrained to implement error correction. The term Noisy
Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems
of 1000 qubits or less. Given NISQ's severe resource constraints, low
reliability, and high variability in physical characteristics such as coherence
time or error rates, it is of pressing importance to map computations onto them
in ways that use resources efficiently and maximize the likelihood of
successful runs.
This paper proposes and evaluates backend compiler approaches to map and
optimize high-level QC programs to execute with high reliability on NISQ
systems with diverse hardware characteristics. Our techniques all start from an
LLVM intermediate representation of the quantum program (such as would be
generated from high-level QC languages like Scaffold) and generate QC
executables runnable on the IBM Q public QC machine. We then use this framework
to implement and evaluate several optimal and heuristic mapping methods. These
methods vary in how they account for the availability of dynamic machine
calibration data, the relative importance of various noise parameters, the
different possible routing strategies, and the relative importance of
compile-time scalability versus runtime success. Using real-system
measurements, we show that fine grained spatial and temporal variations in
hardware parameters can be exploited to obtain an average x (and up to
x) improvement in program success rate over the industry standard IBM
Qiskit compiler.Comment: To appear in ASPLOS'1
Full-Stack, Real-System Quantum Computer Studies: Architectural Comparisons and Design Insights
In recent years, Quantum Computing (QC) has progressed to the point where
small working prototypes are available for use. Termed Noisy Intermediate-Scale
Quantum (NISQ) computers, these prototypes are too small for large benchmarks
or even for Quantum Error Correction, but they do have sufficient resources to
run small benchmarks, particularly if compiled with optimizations to make use
of scarce qubits and limited operation counts and coherence times. QC has not
yet, however, settled on a particular preferred device implementation
technology, and indeed different NISQ prototypes implement qubits with very
different physical approaches and therefore widely-varying device and machine
characteristics.
Our work performs a full-stack, benchmark-driven hardware-software analysis
of QC systems. We evaluate QC architectural possibilities, software-visible
gates, and software optimizations to tackle fundamental design questions about
gate set choices, communication topology, the factors affecting benchmark
performance and compiler optimizations. In order to answer key cross-technology
and cross-platform design questions, our work has built the first top-to-bottom
toolflow to target different qubit device technologies, including
superconducting and trapped ion qubits which are the current QC front-runners.
We use our toolflow, TriQ, to conduct {\em real-system} measurements on 7
running QC prototypes from 3 different groups, IBM, Rigetti, and University of
Maryland. From these real-system experiences at QC's hardware-software
interface, we make observations about native and software-visible gates for
different QC technologies, communication topologies, and the value of
noise-aware compilation even on lower-noise platforms. This is the largest
cross-platform real-system QC study performed thus far; its results have the
potential to inform both QC device and compiler design going forward.Comment: Preprint of a publication in ISCA 201
Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers
Recent developments in engineering and algorithms have made real-world
applications in quantum computing possible in the near future. Existing quantum
programming languages and compilers use a quantum assembly language composed of
1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this
quantum assembly to electric signals (called control pulses) that implement the
specified computation on specific physical devices. However, there is a
mismatch between the operations defined by the 1- and 2-qubit logical ISA and
their underlying physical implementation, so the current practice of directly
translating logical instructions into control pulses results in inefficient,
high-latency programs. To address this inefficiency, we propose a universal
quantum compilation methodology that aggregates multiple logical operations
into larger units that manipulate up to 10 qubits at a time. Our methodology
then optimizes these aggregates by (1) finding commutative intermediate
operations that result in more efficient schedules and (2) creating custom
control pulses optimized for the aggregate (instead of individual 1- and
2-qubit operations). Compared to the standard gate-based compilation, the
proposed approach realizes a deeper vertical integration of high-level quantum
software and low-level, physical quantum hardware. We evaluate our approach on
important near-term quantum applications on simulations of superconducting
quantum architectures. Our proposed approach provides a mean speedup of
, with a maximum of . Because latency directly affects the
feasibility of quantum computation, our results not only improve performance
but also have the potential to enable quantum computation sooner than otherwise
possible.Comment: 13 pages, to apper in ASPLO
Optimization of Circuits for IBM's five-qubit Quantum Computers
IBM has made several quantum computers available to researchers around the
world via cloud services. Two architectures with five qubits, one with 16, and
one with 20 qubits are available to run experiments. The IBM architectures
implement gates from the Clifford+T gate library. However, each architecture
only implements a subset of the possible CNOT gates. In this paper, we show how
Clifford+T circuits can efficiently be mapped into the two IBM quantum
computers with 5 qubits. We further present an algorithm and a set of circuit
identities that may be used to optimize the Clifford+T circuits in terms of
gate count and number of levels. It is further shown that the optimized
circuits can considerably reduce the gate count and number of levels and thus
produce results with better fidelity
Demonstration of quantum volume 64 on a superconducting quantum computing system
We improve the quality of quantum circuits on superconducting quantum
computing systems, as measured by the quantum volume, with a combination of
dynamical decoupling, compiler optimizations, shorter two-qubit gates, and
excited state promoted readout. This result shows that the path to larger
quantum volume systems requires the simultaneous increase of coherence, control
gate fidelities, measurement fidelities, and smarter software which takes into
account hardware details, thereby demonstrating the need to continue to
co-design the software and hardware stack for the foreseeable future.Comment: Fixed typo in author list. Added references [38], [49] and [52
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