Damage Tolerant Active Contro l: Concept and State of the Art

Damage tolerant active control is a new research area relating to fault tolerant control design applied to mechanical structures. It encompasses several techniques already used to design controllers and to detect and to diagnose faults, as well to monitor structural integrity. Brief reviews of the common intersections of these areas are presented, with the purpose to clarify its relations and also to justify the new controller design paradigm. Some examples help to better understand the role of the new area

Optimal fault-tolerant placement of relay nodes in a mission critical wireless network

The operations of many critical infrastructures (e.g., airports) heavily depend on proper functioning of the radio communication network supporting operations. As a result, such a communication network is indeed a mission-critical communication network that needs adequate protection from external electromagnetic interferences. This is usually done through radiogoniometers. Basically, by using at least three suitably deployed radiogoniometers and a gateway gathering information from them, sources of electromagnetic emissions that are not supposed to be present in the monitored area can be localised. Typically, relay nodes are used to connect radiogoniometers to the gateway. As a result, some degree of fault-tolerance for the network of relay nodes is essential in order to offer a reliable monitoring. On the other hand, deployment of relay nodes is typically quite expensive. As a result, we have two conflicting requirements: minimise costs while guaranteeing a given fault-tolerance. In this paper address the problem of computing a deployment for relay nodes that minimises the relay node network cost while at the same time guaranteeing proper working of the network even when some of the relay nodes (up to a given maximum number) become faulty (fault-tolerance). We show that the above problem can be formulated as a Mixed Integer Linear Programming (MILP) as well as a Pseudo-Boolean Satisfiability (PB-SAT) optimisation problem and present experimental results com- paring the two approaches on realistic scenarios

Towards Opportunistic Data Dissemination in Mobile Phone Sensor Networks

Recently, there has been a growing interest within the research community in developing opportunistic routing protocols. Many schemes have been proposed; however, they differ greatly in assumptions and in type of network for which they are evaluated. As a result, researchers have an ambiguous understanding of how these schemes compare against each other in their specific applications. To investigate the performance of existing opportunistic routing algorithms in realistic scenarios, we propose a heterogeneous architecture including fixed infrastructure, mobile infrastructure, and mobile nodes. The proposed architecture focuses on how to utilize the available, low cost short-range radios of mobile phones for data gathering and dissemination. We also propose a new realistic mobility model and metrics. Existing opportunistic routing protocols are simulated and evaluated with the proposed heterogeneous architecture, mobility models, and transmission interfaces. Results show that some protocols suffer long time-to-live (TTL), while others suffer short TTL. We show that heterogeneous sensor network architectures need heterogeneous routing algorithms, such as a combination of Epidemic and Spray and Wait

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints