An Analytic Calculation Method for Delay Time of RC-class Interconnects

Abstract | This paper presents an analytic 3 rd order calculation method, without simulations, for delay time of RC-class circuits, which can be conveniently used to model on-chip interconnects. While the proposed method requires comparable evaluation time to the previous 2 nd order calculation method, it ensures more accurate results than those of 2 nd order method. The proposed analytic delay calculation method guarantees allowable error tolerance when compared to the results obtained from the AWE technique or HSPICE and has better performance in evaluation time as well as numerical stability. The rst algorithm of the proposed method requires 7 moments for the 3 rd order approximation and yields accurate delay time approximation. The second algorithm requires 5 moments for the 3 rd order approximation and results in shorter evaluation time, the accuracy of which maybeless than the rst algorithm. I